Location: Da Nang/ Ho Chi Minh City
Employment Type: Full-time
About the Opportunity
On behalf of our client we are hiring a Physical Design Engineer to support their growing ASIC/SoC team. Our client is a fast-growing technology organization specializing in Semiconductor VLSI and Embedded Systems with international operations across Singapore and Vietnam.
Joining the team as a Physical Design Engineer you will drive the full physical design flow for advanced high-performance data processing chips. You will be responsible for optimizing PPA (Power Performance and Area) and resolving complex timing challenges to ensure successful tape-outs
Key Responsibilities
Execute the complete Physical Design flow encompassing Floorplanning Placement Clock Tree Synthesis (CTS) Routing Static Timing Analysis (STA) and Sign-off procedures (DRC/LVS/EM/IR).
Contribute to high-level SoC/ASIC tape-outs by optimizing design parameters and addressing technical timing hurdles.
Develop and implement automation scripts to enhance design efficiency and robustness.
Job Requirements
Technical skills:
A minimum of 3 years of professional experience in Physical Design specifically for ASIC or SoC projects.
Proficiency in modern Electronic Design Automation (EDA) tools such as Cadence Innovus Synopsys ICC2 or Fusion Compiler (FC).
Deep technical knowledge of Static Timing Analysis (STA) Place and Route (PnR) floorplanning and low-power design methodologies.
Hands-on experience with scripting languages including TCL Python and Shell.
Soft skills:
Basic English communication skills.
Ability to work effectively within a professional friendly and supportive technical environment.
Commitment to continuous learning and technical career growth
Benefits
Competitive salary package including a 14th-month salary/performance bonuses paid twice per year.
Full social health and unemployment insurance coverage calculated on a 100% salary base.
Provision for travel-related allowances.
Direct involvement in advanced high-performance SoC and ASIC design programs.
Dedicated technical mentorship and clearly defined pathways for long-term career advancement.
Structured annual reviews focused on transparent growth and professional development discussions.
An international professional and friendly working environment.
Active participation in team-building activities internal events and company-wide engagement programs.
How to Apply
Send your updated resume to
For more details contact:
Anh Vu (Anna) - Recruitment Consultant
Email:
Phone/Zalo:
Location: Da Nang/ Ho Chi Minh CityEmployment Type: Full-timeAbout the OpportunityOn behalf of our client we are hiring a Physical Design Engineer to support their growing ASIC/SoC team. Our client is a fast-growing technology organization specializing in Semiconductor VLSI and Embedded Systems with...
Location: Da Nang/ Ho Chi Minh City
Employment Type: Full-time
About the Opportunity
On behalf of our client we are hiring a Physical Design Engineer to support their growing ASIC/SoC team. Our client is a fast-growing technology organization specializing in Semiconductor VLSI and Embedded Systems with international operations across Singapore and Vietnam.
Joining the team as a Physical Design Engineer you will drive the full physical design flow for advanced high-performance data processing chips. You will be responsible for optimizing PPA (Power Performance and Area) and resolving complex timing challenges to ensure successful tape-outs
Key Responsibilities
Execute the complete Physical Design flow encompassing Floorplanning Placement Clock Tree Synthesis (CTS) Routing Static Timing Analysis (STA) and Sign-off procedures (DRC/LVS/EM/IR).
Contribute to high-level SoC/ASIC tape-outs by optimizing design parameters and addressing technical timing hurdles.
Develop and implement automation scripts to enhance design efficiency and robustness.
Job Requirements
Technical skills:
A minimum of 3 years of professional experience in Physical Design specifically for ASIC or SoC projects.
Proficiency in modern Electronic Design Automation (EDA) tools such as Cadence Innovus Synopsys ICC2 or Fusion Compiler (FC).
Deep technical knowledge of Static Timing Analysis (STA) Place and Route (PnR) floorplanning and low-power design methodologies.
Hands-on experience with scripting languages including TCL Python and Shell.
Soft skills:
Basic English communication skills.
Ability to work effectively within a professional friendly and supportive technical environment.
Commitment to continuous learning and technical career growth
Benefits
Competitive salary package including a 14th-month salary/performance bonuses paid twice per year.
Full social health and unemployment insurance coverage calculated on a 100% salary base.
Provision for travel-related allowances.
Direct involvement in advanced high-performance SoC and ASIC design programs.
Dedicated technical mentorship and clearly defined pathways for long-term career advancement.
Structured annual reviews focused on transparent growth and professional development discussions.
An international professional and friendly working environment.
Active participation in team-building activities internal events and company-wide engagement programs.
How to Apply
Send your updated resume to
For more details contact:
Anh Vu (Anna) - Recruitment Consultant
Email:
Phone/Zalo:
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