Design For Test

Aloha Consulting Group

Job Location:

Ho Chi Minh City - Vietnam

Salary: Not Disclosed

Experience Required: 5-7years

Posted on: Yesterday

Vacancies: 1 Vacancy

Job Summary

ACG3442JOB

Our client is a technology company that is looking for a qualified candidate to join their firm.

Perform end-to-end DFT engineering tasks including DFT audit scan logic MBIST and BSCAN insertion.
Implement hardware Design-for-Test (DFT) features to support ATE in-system testing debugging and diagnostics.
Develop innovative DFT IP in collaboration with cross-functional teams and play a key role in full-chip integration of testability features within RTL.
Work closely with design design-verification and physical design teams to enable seamless integration and validation of test logic throughout all phases of design and back-end implementation flow.
Analyze timing reports related to DFT logic and provide actionable solutions.
Perform gate-level simulations with and without timing annotations to ensure design robustness.
Diagnose and analyze data logs during silicon bring-up to finalize prototype test patterns.
Lead the development of innovative hardware DFT strategies for new silicon device models including bare die and stacked die driving reusable test and debug approaches.

Requirements

Minimum 5 years of experience in DFT engineering.
Strong understanding of DFT concepts and clock architecture.
Hands-on experience with whole-chip DFT implementation using various flows including Tessent Shell flow and hybrid/mixed-vendor flows.
Solid knowledge of industry standards and practices in DFT including ATPG JTAG MBIST and trade-offs between test quality and test time.
Experience developing DFT specifications and driving DFT architecture and methodology for designs.
Expertise in debugging compressed ATPG patterns MBIST and JTAG/1500-related issues.
Ability to build timing constraints (SDC) for SCAN MBIST and IJTAG modes and analyze timing reports.
Knowledge of functional safety clock domain crossing (CDC) analysis logic synthesis and scan insertion.
Strong problem-solving skills and ability to work collaboratively with cross-functional teams.

Contact: Giau Nguyen

Due to the immense number of applications only shortlisted candidates will be contacted.

Required Skills:

Must-have Minimum 5 years of experience in senior leadership roles such as HR Director CHRO COO or equivalent in large-scale organizations (500 employees). Strong expertise in human resources management business administration or related fields. Good command of English (both written and spoken). Nice-to-have Strong leadership strategic thinking and analytical capabilities. Excellent communication and presentation skills with the ability to influence stakeholders. Familiarity with AI applications in HR management and operations. An international education background is a plus. Contact: Ha Hoang Due to the immense number of applications only shortlisted candidates will be contacted.

ACG3442JOBOur client is a technology company that is looking for a qualified candidate to join their firm.Perform end-to-end DFT engineering tasks including DFT audit scan logic MBIST and BSCAN insertion.Implement hardware Design-for-Test (DFT) features to support ATE in-system testing debugging and...

ACG3442JOB

Our client is a technology company that is looking for a qualified candidate to join their firm.

Perform end-to-end DFT engineering tasks including DFT audit scan logic MBIST and BSCAN insertion.
Implement hardware Design-for-Test (DFT) features to support ATE in-system testing debugging and diagnostics.
Develop innovative DFT IP in collaboration with cross-functional teams and play a key role in full-chip integration of testability features within RTL.
Work closely with design design-verification and physical design teams to enable seamless integration and validation of test logic throughout all phases of design and back-end implementation flow.
Analyze timing reports related to DFT logic and provide actionable solutions.
Perform gate-level simulations with and without timing annotations to ensure design robustness.
Diagnose and analyze data logs during silicon bring-up to finalize prototype test patterns.
Lead the development of innovative hardware DFT strategies for new silicon device models including bare die and stacked die driving reusable test and debug approaches.

Requirements

Minimum 5 years of experience in DFT engineering.
Strong understanding of DFT concepts and clock architecture.
Hands-on experience with whole-chip DFT implementation using various flows including Tessent Shell flow and hybrid/mixed-vendor flows.
Solid knowledge of industry standards and practices in DFT including ATPG JTAG MBIST and trade-offs between test quality and test time.
Experience developing DFT specifications and driving DFT architecture and methodology for designs.
Expertise in debugging compressed ATPG patterns MBIST and JTAG/1500-related issues.
Ability to build timing constraints (SDC) for SCAN MBIST and IJTAG modes and analyze timing reports.
Knowledge of functional safety clock domain crossing (CDC) analysis logic synthesis and scan insertion.
Strong problem-solving skills and ability to work collaboratively with cross-functional teams.