Sr Physical Design Engineer STA Timing - Onsite
Sr Physical Design Engineer STA Timing - Onsite
Posted on :
05-04-2025
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1 Vacancy
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Job Description
Job Title: Sr STA Engineer
Fulltime / Contract
Work Status: US Citizen / US Permanent Resident
Location: Irvine CA Onsite) no remote/Hybrid
As a Senior Digital Physical Design Engineer you will work as a team member on block level and chip level physical design tasks. You will perform P&R implementation of highperformance SoC designs including logic synthesis floorplan and powerplan clock tree synthesis static timing analysis IR drop analysis EM DRC and physical verification in advanced technology nodes such as 14/12 nm FinFET. You will work closely with a multisite team of SoC design verification and software engineers with the goal of delivering productionquality designs for wireless communications products.
Key Responsibilities
Physical implementation RTL to GDSII at block and chip level for complex SoC devices
Run P&R and timing tools to produce layout that meets density and performance goals
Actively assist in tape out process including DRC LVS and ERC verification flows
Work with DRC/LVS and extraction flow and rules decks using Calibre
Expert level knowledge in Cadence Innovus Genus Tempus and Voltus environments
Experience in Cadence Stylus and Cadence Virtuoso Design Framework desired
Interact with tool vendors to drive tool fixes and flow improvements
Handson experience with scripting (Python Tcl C)
Excellent verbal and written communication skills
BSEE or MSEE with a minimum of 10 years of backend physical design experience required
The anticipated annual base salary for this position is between $145000 to $175000 which also includes a comprehensive benefits package.
FullTime Benefits:
15 days of PTO per calendar year
10 paid Holidays per calendar year
Comprehensive Medical Benefits: Company pays 80 of medical premium for Employee and Dependents
Dental & Vision: Company pays 50 of Dental and Vision premiums for Employee and Dependents
Voluntary Benefits: Dental & Vision Insurance FSA HSA and Gap Insurance
Employee Assistant Program (EAP)
401k Traditional & Roth
Life/AD&D and LongTerm Disability
Tuition reimbursement
Equal Opportunity Policy Statement
Encore Semi Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race religion creed color age sex sexual orientation gender gender identity or expression national origin genetics ancestry marital status civil union status medical condition disability (mental and physical) military and veteran status pregnancy childbirth and related medical conditions or any other characteristic protected by applicable federal state or local laws and ordinances.
Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.
Our management team is dedicated to this policy with respect to recruitment hiring placement promotion transfer training compensation benefits employee activities and general treatment during employment.
Fulltime / Contract
Work Status: US Citizen / US Permanent Resident
Location: Irvine CA Onsite) no remote/Hybrid
As a Senior Digital Physical Design Engineer you will work as a team member on block level and chip level physical design tasks. You will perform P&R implementation of highperformance SoC designs including logic synthesis floorplan and powerplan clock tree synthesis static timing analysis IR drop analysis EM DRC and physical verification in advanced technology nodes such as 14/12 nm FinFET. You will work closely with a multisite team of SoC design verification and software engineers with the goal of delivering productionquality designs for wireless communications products.
Key Responsibilities
Physical implementation RTL to GDSII at block and chip level for complex SoC devices
Run P&R and timing tools to produce layout that meets density and performance goals
Actively assist in tape out process including DRC LVS and ERC verification flows
Work with DRC/LVS and extraction flow and rules decks using Calibre
Expert level knowledge in Cadence Innovus Genus Tempus and Voltus environments
Experience in Cadence Stylus and Cadence Virtuoso Design Framework desired
Interact with tool vendors to drive tool fixes and flow improvements
Handson experience with scripting (Python Tcl C)
Excellent verbal and written communication skills
BSEE or MSEE with a minimum of 10 years of backend physical design experience required
The anticipated annual base salary for this position is between $145000 to $175000 which also includes a comprehensive benefits package.
FullTime Benefits:
15 days of PTO per calendar year
10 paid Holidays per calendar year
Comprehensive Medical Benefits: Company pays 80 of medical premium for Employee and Dependents
Dental & Vision: Company pays 50 of Dental and Vision premiums for Employee and Dependents
Voluntary Benefits: Dental & Vision Insurance FSA HSA and Gap Insurance
Employee Assistant Program (EAP)
401k Traditional & Roth
Life/AD&D and LongTerm Disability
Tuition reimbursement
Equal Opportunity Policy Statement
Encore Semi Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race religion creed color age sex sexual orientation gender gender identity or expression national origin genetics ancestry marital status civil union status medical condition disability (mental and physical) military and veteran status pregnancy childbirth and related medical conditions or any other characteristic protected by applicable federal state or local laws and ordinances.
Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.
Our management team is dedicated to this policy with respect to recruitment hiring placement promotion transfer training compensation benefits employee activities and general treatment during employment.
Required Experience:
Senior IC
Employment Type
Full Time
Key Skills
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