Rambus a premier chip and silicon IP provider is seeking to hire an exceptional Senior/Lead Design Verification Engineer to join our Memory Controller IP team in Bangalore India. The successful candidate will participate in pre-silicon RTL Verification activities related to Memory Controller SoftIP development on leading-edge DDR HBM GDDR and LPDDR DRAM controller technologies. This is a Full Time position reporting to a local onsite manager of India Memory Controller Verification.
Rambus offers a flexible work environment embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite while also allowing for two days of remote work.
Duties in this position will include:
Testbench and test sequence development for verification of new controller technologies and features
Functional coverage planning coverage item coding and test suite augmentation to achieve Functional Coverage
Regression test development monitoring debug/triage and correction to test environment sequences debug of controller RTL design
Development & support of Verification environment scripting and capabilities
Bachelors Degree or above in EE/CS minimum 5 years experience with HDL logic Design-Verification
System Verilog testbench Verilog/System Verilog logic design/RTL fluency a must
Pre-existing Experience / familiarity with DDR DRAM technology a strong preference
Working experience with Python and TCL scripting languages preferred
Required Experience:
IC
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