Lead Analog Layout Engineer (10 15 Years) Bengaluru
About the Role
We are seeking a Lead Analog Layout Engineer to spearhead the custom layout implementation for analog/mixed-signal (AMS) modules and custom-digital blocks within our SoC this role you will be responsible for delivering high-quality physical verification-clean layouts while leading a team of junior engineers to meet aggressive project schedules. As Layout Lead you will:
Responsibilities
-
Be responsible for Physical Verification clean Layout.
-
Craft layout of AMS IPs by doing proper floorplan routing addressing constraints like matching parasitics signal flow power distribution area etc. and review with Analog Design team
-
Lead and mentor a team of junior layout engineers reviewing their work and ensuring quality.
-
Work closely with design team to plan layout schedule discuss and align on trade-offs etc.
Skills/knowledge required
-
Using CAD tools to deliver correct and robust layout.
-
Cadence Virtuoso LayoutXL ) tool expertise for layout and Mentor (calibre suite for DRC LVS verification generating extracted view for post-layout sims.
-
Experience in FinFet/Planar Si CMOS technologies is a MUST. SiGe/GaN is a plus.
-
Extensive PAD Ring and Chip-top level layout experience with integration of Analog IPs Digital GDS etc.
-
Knowledge of design for manufacturability (DFM) principles. - Ability to troubleshoot and resolve layout-related issues effectively.
-
Expertise in layout of high-speed SERDES RF and/or PM modules is a must
Qualifications required
-
B.E./ or M.E./ in Electronics Electrical or related field.
#LI-VA1
Lead Analog Layout Engineer (10 15 Years) Bengaluru About the Role We are seeking a Lead Analog Layout Engineer to spearhead the custom layout implementation for analog/mixed-signal (AMS) modules and custom-digital blocks within our SoC this role you will be responsible for delivering high...
Lead Analog Layout Engineer (10 15 Years) Bengaluru
About the Role
We are seeking a Lead Analog Layout Engineer to spearhead the custom layout implementation for analog/mixed-signal (AMS) modules and custom-digital blocks within our SoC this role you will be responsible for delivering high-quality physical verification-clean layouts while leading a team of junior engineers to meet aggressive project schedules. As Layout Lead you will:
Responsibilities
-
Be responsible for Physical Verification clean Layout.
-
Craft layout of AMS IPs by doing proper floorplan routing addressing constraints like matching parasitics signal flow power distribution area etc. and review with Analog Design team
-
Lead and mentor a team of junior layout engineers reviewing their work and ensuring quality.
-
Work closely with design team to plan layout schedule discuss and align on trade-offs etc.
Skills/knowledge required
-
Using CAD tools to deliver correct and robust layout.
-
Cadence Virtuoso LayoutXL ) tool expertise for layout and Mentor (calibre suite for DRC LVS verification generating extracted view for post-layout sims.
-
Experience in FinFet/Planar Si CMOS technologies is a MUST. SiGe/GaN is a plus.
-
Extensive PAD Ring and Chip-top level layout experience with integration of Analog IPs Digital GDS etc.
-
Knowledge of design for manufacturability (DFM) principles. - Ability to troubleshoot and resolve layout-related issues effectively.
-
Expertise in layout of high-speed SERDES RF and/or PM modules is a must
Qualifications required
-
B.E./ or M.E./ in Electronics Electrical or related field.
#LI-VA1
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