RET LayoutMask Engineer

Change the world. Love your job.
Texas Instruments is in an exciting era of growth and innovation and our Advanced Technology Development (ATD) organization is at the center of it developing the 28nm process technologies that will define TIs next generation of analog and embedded processing capabilities. As part of ATD you wont just support production youll create the technology that makes it possible. Our engineers are working at the leading edge of computational lithography Resolution Enhancement Techniques and advanced process integration solving the fundamental patterning and process challenges that determine whether a 28nm technology can be manufactured at scale and at yield. The work done in ATD directly enables fabs that will manufacture tens of millions of analog and embedded processing chips every day supporting customer demand for decades to come. Were committed to responsible sustainable semiconductor manufacturing and to building a diverse technically excellent team that drives meaningful impact across the this role youll work at the intersection of fundamental research and high-volume manufacturing turning process innovations into production-ready technologies that power electronics everywhere.

As a Resolution Enhancement Techniques (RET) Layout Engineer you will architect new TI products and make our customers visions a reality. You will define design model implement and document analog digital and RF integrated circuits (ICs).

Responsibilities will include but are not limited to:

• Create layouts for setup evaluation and monitor of lithography/etch wafer processes.
  • Work with fabrication process engineering and integration teams to determine specifications.
  • Use design rules and/or existing layouts to create/modify test features.
  • Maintain a list of measurement coordinate locations.
  • Support and interaction for all fabs and technologies required.
• Create layouts for OPC development/monitor.
  • Work with other RET engineers on layout and floor plan of test reticles for OPC model calibration and recipe development.
  • Work with RET engineers to layout scribe modules for OPC model calibration/testing.
• Create layouts for reticle measurement and disposition.
  • Work with other RET engineers and the PDK team to define specifications.
  • Maintain a list of measurement coordinate locations.
  • Work with RET scribe and design teams to create rules for layout placement.
• Develop and implement automation for producing layouts.

Minimum qualifications:

• Bachelors in Electrical Engineering Physics Computer Science Chemistry or related degree
• Proficiency with EDA layout tools (Cadence suite Synopsys etc.) and scripting (e.g. Python SKILL Perl)
• 5 years of experience in Layout/Mask design.

Preferred qualifications:

• Hands-on experience in design or PDK development with direct experience at a semiconductor company
• Excellent problem-solving analytical and communication skills for cross-team collaboration
• Experience working with PG flows
• Strong lithography knowledge
• OPC experience