Memory Interface PHY IP, Design Engineering Architect

At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.

A Design Engineering Architect provides the technical leadership needed to translate evolving standards and customer requirements into scalable highquality IP architectures. This role reduces execution risk accelerates customer engagements and strengthens longterm product competitiveness.

Design Engineering Architect Roles & Responsibilities

• Contribute to PHY architecture development with deep understanding of memory interface PHY IPs (e.g. DDR LPDDR) including electrical timing power and protocol considerations
• Drive architecture decisions aligned with JEDEC standards protocols and compliance requirements
• Good understanding of PHY/IO circuit architecture including TX/RX clocking termination power delivery and signal integrity tradeoffs
• Act as a customerfacing technical architect during presales evaluations and postdelivery support clearly articulating architecture choices and tradeoffs
• Collaborate closely with Sales Marketing and Program teams to support customer engagements RFIs and technical proposals
• Provide expertlevel IP support to customers including architecture clarification feature customization
• Work crossfunctionally with design verification layout and silicon validation teams to ensure architectural intent is correctly implemented
• Review and guide architecture specifications design reviews and technical documentation
• Influence product and technology roadmap planning by identifying future standards protocol evolution and customerdriven requirements
• Demonstrate strong communication accountability and technical ownership across internal and external interactions

Required Qualifications

• M.S. degree in Electrical Engineering Computer Engineering or related field
• Minimum 15 years of industry experience in memory interface PHY highspeed IO or related domains
• Strong background in memory interface PHYs JEDEC standards and protocols
• Proven ability to own customerfacing technical engagements and drive issues to closure
• Excellent written and verbal communication skills

The annual salary range for California is $136500 to $253500. You may also be eligible to receive incentive compensation: bonus equity and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications skill level competencies and work location. Our benefits programs include: paid vacation and paid holidays 401(k) plan with employer match employee stock purchase plan a variety of medical dental and vision plan options and more.

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