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Circuits Physical Design Engineer LibraryProcess Monitor
Job Location:
Job Location:
Beaverton, OR - USA
Monthly Salary:
Not provided by the employer
Monthly Salary:
Posted:
11 July 2026 (30+ days ago)
Posted:
Application Deadline:
8 October 2026
Application Deadline:
Vacancies:
1 Vacancy
Vacancies:
Job Summary
Do you have a passion for crafting entirely new solutions As part of our Digital Design Engineering group youll take imaginative and revolutionary ideas and determine how to turn them into reality! You and your team will apply engineering fundamentals and start from scratch if needed bringing forward-thinking ideas to the real world. Your efforts will be groundbreaking. Your efforts will be groundbreaking. Join us and youll help design the tools that allow us to bring customers experiences theyve never before envisioned! We have an extraordinary opportunity for Physical Design this highly visible role you will be at the heart of a processor design effort working with foundation IP developers on silicon validation making a critical impact delivering products to market quickly.
Imagine yourself at the center of our SOC design effort collaborating with all fields playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new insights as well as work with a team of hardworking engineers. As a Physical Design Engineer you will be responsible for fully comprehensive library EDA view validation by taking a Pu0026R block through RTL to GDS steps. This will include physical synthesis placement CTS routing timing optimization leakage recovery and closure u0026 signoff. You will also be responsible for PT/spice correlation signal and power EM analysis IR analysis and PDV. You will also architect and compose blocks consisting of library cells for complete Silicon Validation.
BS and a minimum of 2 years of relevant industry experience.
We are looking for applicants with 2 years of proven experience and strong understanding of the RTL2GDSII flow and concepts related to synthesis place u0026 route CTS timing convergence layout with development of block/partitions for silicon validation of foundation with ASIC integration flows including power distribution global signal planning I/O planning and hard IP integration is a strong with tapeout of partitions and Verification Flows like LEQ IR/EM Timing and DFM closure is a strong -on experience with ECO implementation both functional and timing closure is a strong with DFT insertion and multi-mode timing constraints is a strong scripting skills using Perl/ written/verbal communication skills.
Imagine yourself at the center of our SOC design effort collaborating with all fields playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new insights as well as work with a team of hardworking engineers. As a Physical Design Engineer you will be responsible for fully comprehensive library EDA view validation by taking a Pu0026R block through RTL to GDS steps. This will include physical synthesis placement CTS routing timing optimization leakage recovery and closure u0026 signoff. You will also be responsible for PT/spice correlation signal and power EM analysis IR analysis and PDV. You will also architect and compose blocks consisting of library cells for complete Silicon Validation.
BS and a minimum of 2 years of relevant industry experience.
We are looking for applicants with 2 years of proven experience and strong understanding of the RTL2GDSII flow and concepts related to synthesis place u0026 route CTS timing convergence layout with development of block/partitions for silicon validation of foundation with ASIC integration flows including power distribution global signal planning I/O planning and hard IP integration is a strong with tapeout of partitions and Verification Flows like LEQ IR/EM Timing and DFM closure is a strong -on experience with ECO implementation both functional and timing closure is a strong with DFT insertion and multi-mode timing constraints is a strong scripting skills using Perl/ written/verbal communication skills.
Required Experience:
IC
About Company
Ask Siri to name the most successful company in the world and it might respond: Apple. And it's not just out of familial pride. Apple consistently ranks highly in profit, revenue, market capitalization, and consumer cachet. In 2018, the company became the first reach a trillion dollar ... View more
