Contract Hardware Engineer Mid

Duties: Location: Remote (Within USA) Experience level: 7 to 15 Years. Candidate Roles and Responsibilities NOTE : This is reference to an Analog layout engineer having experiences in Analog Layout Physical verification Calibre LVS DRC ERC 10nm or less FinFET . Layout Design Engineer to develop digital and analog layouts that meets performance power and area objectives. Layout designer tasks include: translating highly hierarchical designs into layout compliant to all checking: LVS DRC ERC Softcheck. Target metrics are highperformance and low power so detailed attention to resistance and capacitance is a necessity. Experience with mitigation of layout design effects such as nwell proximity effect diffusion spacing effect length of diffusion effect are also key. Knowledgeable in device matching pitch matching balancing and shielding of critical devices. Experience with multi patterning and deep submicron requirements. Experience building a sufficient power distribution grid. Able to work in a dynamic and diverse team environment and meet necessary deadlines. Able to independently perform efficient debugging of Calibre verification results using RVE with ability to implement timely layout corrections of results while maintaining the integrity of the design. Tool usage includes Cadence Virtuoso XL and Calibre Technology 10nm or smaller.

Skills: Location: Remote (Within USA) Experience level: 7 to 15 Years. Candidate Roles and Responsibilities NOTE : This is reference to an Analog layout engineer having experiences in Analog Layout Physical verification Calibre LVS DRC ERC 10nm or less FinFET . Layout Design Engineer to develop digital and analog layouts that meets performance power and area objectives. Layout designer tasks include: translating highly hierarchical designs into layout compliant to all checking: LVS DRC ERC Softcheck. Target metrics are highperformance and low power so detailed attention to resistance and capacitance is a necessity. Experience with mitigation of layout design effects such as nwell proximity effect diffusion spacing effect length of diffusion effect are also key. Knowledgeable in device matching pitch matching balancing and shielding of critical devices. Experience with multi patterning and deep submicron requirements. Experience building a sufficient power distribution grid. Able to work in a dynamic and diverse team environment and meet necessary deadlines. Able to independently perform efficient debugging of Calibre verification results using RVE with ability to implement timely layout corrections of results while maintaining the integrity of the design. Tool usage includes Cadence Virtuoso XL and Calibre Technology 10nm or smaller.

Education: Bachelors

Required Skills: DIVERSE TEAMMETRICSTRANSLATINGCADENCEPOWER DISTRIBUTION
Additional Skills: VIRTUOSOMITIGATIONANALOG

Minimum Degree Required: Bachelors Degree
Hours Per Day: 8.00
Hours Per Week: 40.00
Languages: English( Speak Read Write )
Department: Regional Recruiting Services : 7134
Job Category: IT