Design Engineer – Physical II

The Design Engineer Physical II will be responsible for physical verification and signoff activities for complex semiconductor designs. The role involves ensuring that layouts meet foundry requirements design rules and signoff criteria prior to tape-out. The engineer will collaborate with physical design layout and technology teams to ensure robust verification flows and resolve layout issues efficiently.

Physical Verification & Signoff

• Perform physical verification including DRC LVS ERC and DFM checks using industry-standard verification tools.

• Execute signoff verification flows for complex designs across hierarchical and flat methodologies.

• Analyze verification results and work closely with layout and design teams to resolve violations.

Layout Validation

• Validate layout compliance with foundry rules and process requirements.

• Ensure adherence to design rule checks and manufacturability constraints before tape-out.

Parasitic Extraction

• Execute parasitic extraction (PEX) and validate extraction results for accuracy and completeness.

• Support timing and signal integrity teams with extracted data for analysis.

Automation & Flow Development

• Develop and maintain automation scripts using Tcl Python or Perl to streamline physical verification flows.

• Improve verification runsets automation frameworks and regression flows.

Technology & Design Enablement

• Work with design enablement kits technology files and runsets provided by foundries.

• Contribute to verification methodology improvements and documentation.

Cross-Functional Collaboration

• Work with physical design layout timing and signoff teams to resolve design issues.

• Participate in debugging complex layout problems and providing verification support during tape-out.

• Strong hands-on experience in physical verification and signoff flows for advanced semiconductor nodes.

Experience with the following tools:

• Calibre (DRC / LVS / ERC / DFM)

• ICV (IC Validator)

• Pegasus (optional but beneficial)

• Strong understanding of foundry design rules and signoff requirements

• Knowledge of hierarchical and flat verification strategies

• Experience with parasitic extraction (PEX) and extraction methodologies

• Familiarity with design enablement kits and runsets

• Proficiency in Tcl Python or Perl for flow automation and verification improvements

• Strong analytical and debugging skills

• Ability to work across cross-functional engineering teams

• Good written and verbal communication skills

• Ability to work within tight project timelines and tape-out schedules

• / MS / in Electronics VLSI Microelectronics or related discipline
  
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