DFT Engineer

Job Summary

We are looking for a skilled Design for Test (DFT) Lead Engineer with 4 6 years of hands-on experience in ASIC/SoC development. The ideal candidate will drive DFT architecture ATPG execution and test coverage improvement while collaborating closely with design physical implementation and verification teams. This role involves technical ownership of DFT implementation and mentoring junior engineers within fast-paced semiconductor projects.

• Lead and execute DFT activities for complex ASIC/SoC projects.

• Drive Scan ATPG architecture from specification to implementation.

• Define and implement MBIST architecture based on design requirements.

• Ensure robust and scalable DFT methodologies aligned with project goals.

• Perform ATPG simulations and achieve maximum fault and test coverage.

• Analyze test failures debug issues and provide technical solutions.

• Support pattern generation and ensure adherence to foundry requirements.

• Develop and automate DFT scripts to improve simulation efficiency and predictability.

• Optimize designs for PPA (Power Performance Area) while maintaining test quality.

• Handle ECO implementation related to DFT changes.

• Support post-layout simulations and validation activities.

• Mentor and guide junior DFT engineers.

• Work closely with RTL PD and verification teams for seamless integration.

• Coordinate with EDA vendors and stay updated with evolving DFT tools and methodologies.

• 4 6 years of hands-on experience in DFT for ASIC/SoC designs.

• Strong understanding of Scan ATPG MBIST and test methodologies.

• Experience with industry-standard DFT tools (Synopsys / Cadence / Siemens flows preferred).

• Knowledge of fault models coverage analysis and debugging techniques.

• Exposure to post-layout DFT validation and ECO handling.

• Scripting skills in TCL / Perl / Python for automation.

• Understanding of foundry guidelines and manufacturing test flows.

• Strong analytical and problem-solving ability

• Good communication and cross-functional collaboration

• Ability to take ownership and drive technical deliverables independently

• Experience with advanced technology nodes

• Exposure to low-power DFT techniques

• Prior experience mentoring junior engineers