Job Overview
We are hiring Physical Design (PD) trained fresh graduates who are passionate about VLSI and semiconductor design. This opportunity is ideal for candidates who have completed Physical Design training from reputed VLSI institutes and are eager to start their careers working on advanced ASIC/SoC implementation candidates will gain hands-on exposure to industry-standard PD flows methodologies and tools while working closely with experienced design and implementation teams.
Eligibility Criteria -
in ECE / EEE / E&I or related streams
-
Year of Passing: 2023 or earlier
-
Completed Physical Design / VLSI training from reputed institutes
-
Strong interest in building a career in the VLSI domain
Key Responsibilities -
Support Physical Design activities across ASIC/SoC implementation flow
-
Assist in floorplanning placement CTS routing and timing closure tasks
-
Work with teams to analyze and resolve timing and physical design issues
-
Contribute to design optimization for performance power and area
-
Assist in validation of DRC/LVS and physical verification checks
-
Learn and follow industry-standard PD methodologies and flows
Required Technical Skills -
Strong fundamentals in CMOS and VLSI design flow
-
Knowledge of Physical Design stages:
-
Understanding of timing concepts setup & hold and clock tree basics
-
Exposure to PD tools such as ICC2 / Innovus (preferred)
-
Basic understanding of SDC and timing constraints
-
Familiarity with DRC and LVS concepts
Soft Skills -
Good communication and teamwork abilities
-
Strong analytical and problem-solving mindset
-
High learning agility and interest in semiconductor technologies
Nice to Have -
Hands-on lab or project work during VLSI/PD training
-
Basic scripting knowledge (TCL/Shell/Python)
-
Understanding of complete ASIC implementation flow
#LI-KR1
Job Overview We are hiring Physical Design (PD) trained fresh graduates who are passionate about VLSI and semiconductor design. This opportunity is ideal for candidates who have completed Physical Design training from reputed VLSI institutes and are eager to start their careers working on advanced A...
Job Overview
We are hiring Physical Design (PD) trained fresh graduates who are passionate about VLSI and semiconductor design. This opportunity is ideal for candidates who have completed Physical Design training from reputed VLSI institutes and are eager to start their careers working on advanced ASIC/SoC implementation candidates will gain hands-on exposure to industry-standard PD flows methodologies and tools while working closely with experienced design and implementation teams.
Eligibility Criteria -
in ECE / EEE / E&I or related streams
-
Year of Passing: 2023 or earlier
-
Completed Physical Design / VLSI training from reputed institutes
-
Strong interest in building a career in the VLSI domain
Key Responsibilities -
Support Physical Design activities across ASIC/SoC implementation flow
-
Assist in floorplanning placement CTS routing and timing closure tasks
-
Work with teams to analyze and resolve timing and physical design issues
-
Contribute to design optimization for performance power and area
-
Assist in validation of DRC/LVS and physical verification checks
-
Learn and follow industry-standard PD methodologies and flows
Required Technical Skills -
Strong fundamentals in CMOS and VLSI design flow
-
Knowledge of Physical Design stages:
-
Understanding of timing concepts setup & hold and clock tree basics
-
Exposure to PD tools such as ICC2 / Innovus (preferred)
-
Basic understanding of SDC and timing constraints
-
Familiarity with DRC and LVS concepts
Soft Skills -
Good communication and teamwork abilities
-
Strong analytical and problem-solving mindset
-
High learning agility and interest in semiconductor technologies
Nice to Have -
Hands-on lab or project work during VLSI/PD training
-
Basic scripting knowledge (TCL/Shell/Python)
-
Understanding of complete ASIC implementation flow
#LI-KR1
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