Cortex Consulting P Ltd

Job Title: IP Design Verification (IP DV) Engineer Location: Bangalore Experience: 5 15 Years Job Description We are looking for an experienced IP Design Verification Engineer with strong expertise in verifying high-speed IPs and developing robust verification environm

Job Title: IP Design Verification (IP DV) Engineer Location: Bangalore Experience: 5 15 Years Job Description We are looking for an experienced IP Design Verification Engineer with strong expertise in verifying high-speed IPs and developing robust verification environm

Job Title: DV Engineer (AMBA) Location: Bangalore / Noida Experience: 5 14 Years Job Description We are looking for an experienced Design Verification (DV) Engineer with strong expertise in SystemVerilog UVM and AMBA Protocol Verification. The ideal candidate should have hands-on

Job Title: DV Engineer (AMBA) Location: Bangalore / Noida Experience: 5 14 Years Job Description We are looking for an experienced Design Verification (DV) Engineer with strong expertise in SystemVerilog UVM and AMBA Protocol Verification. The ideal candidate should have hands-on

Job Title: SoC Design Verification (SoC DV) Engineer Location: Bangalore Experience: 5 15 Years Job Description We are looking for an experienced SoC Design Verification Engineer with strong expertise in SystemVerilog/UVM and C programming for ARM-based SoC verificati

Job Title: SoC Design Verification (SoC DV) Engineer Location: Bangalore Experience: 5 15 Years Job Description We are looking for an experienced SoC Design Verification Engineer with strong expertise in SystemVerilog/UVM and C programming for ARM-based SoC verificati

Job Title: IP DV Engineer High-Speed Protocols Experience: 5 10 yrs Location: India Role: Looking for an IP Verification Engineer with strong expertise in high-speed protocols to develop and execute verification for complex IPs. Key Skills: Strong SystemVerilog & UVM e

Job Title: IP DV Engineer High-Speed Protocols Experience: 5 10 yrs Location: India Role: Looking for an IP Verification Engineer with strong expertise in high-speed protocols to develop and execute verification for complex IPs. Key Skills: Strong SystemVerilog & UVM e

Title: SOC DV Engineer with experience in Sensors CPU Debug Architecture Role and Responsibilities: Job Title: SOC Verification Engineer Exp:4 to 6 yrs Location:Bangalore Key Requirements: 4 6 years of SOC Design Verification (DV) experience with a strong focus on GPI

Title: SOC DV Engineer with experience in Sensors CPU Debug Architecture Role and Responsibilities: Job Title: SOC Verification Engineer Exp:4 to 6 yrs Location:Bangalore Key Requirements: 4 6 years of SOC Design Verification (DV) experience with a strong focus on GPI

Job Title: IP DV Engineer High-Speed Protocols Experience: 5 10 yrs Location: India Role: Looking for an IP Verification Engineer with strong expertise in high-speed protocols to develop and execute verification for complex IPs. Key Skills: Strong SystemVerilog & UVM e

Job Title: IP DV Engineer High-Speed Protocols Experience: 5 10 yrs Location: India Role: Looking for an IP Verification Engineer with strong expertise in high-speed protocols to develop and execute verification for complex IPs. Key Skills: Strong SystemVerilog & UVM e

Title: SOC DV Engineer with experience in Sensors CPU Debug Architecture Role and Responsibilities: Job Title: SOC Verification Engineer Exp:4 to 6 yrs Location:Bangalore Key Requirements: 4 6 years of SOC Design Verification (DV) experience with a strong focus on GPI

Title: SOC DV Engineer with experience in Sensors CPU Debug Architecture Role and Responsibilities: Job Title: SOC Verification Engineer Exp:4 to 6 yrs Location:Bangalore Key Requirements: 4 6 years of SOC Design Verification (DV) experience with a strong focus on GPI

: DFX Verification Exp:4 to 10 yrs Location: Bangalore Key Responsibilities Develop and execute verification plans for DFx features including: Scan (stuck-at transition fault) MBIST / LBIST Boundary Scan (JTAG) Memory repair and redundancy Low-power test scenarios Creat

: DFX Verification Exp:4 to 10 yrs Location: Bangalore Key Responsibilities Develop and execute verification plans for DFx features including: Scan (stuck-at transition fault) MBIST / LBIST Boundary Scan (JTAG) Memory repair and redundancy Low-power test scenarios Creat

: DFX Verification Exp:4 to 10 yrs Location: Bangalore Key Responsibilities Develop and execute verification plans for DFx features including: Scan (stuck-at transition fault) MBIST / LBIST Boundary Scan (JTAG) Memory repair and redundancy Low-power test scenarios Creat

: DFX Verification Exp:4 to 10 yrs Location: Bangalore Key Responsibilities Develop and execute verification plans for DFx features including: Scan (stuck-at transition fault) MBIST / LBIST Boundary Scan (JTAG) Memory repair and redundancy Low-power test scenarios Creat

Role: PD PNR Engineer Experience: 5 Years Location: Pune Job Description: We are looking for an experienced Physical Design / PNR Engineer with 5 years of hands-on experience in block/full-chip physical design implementation. Candidate should have strong expertise in Floorpla

Role: PD PNR Engineer Experience: 5 Years Location: Pune Job Description: We are looking for an experienced Physical Design / PNR Engineer with 5 years of hands-on experience in block/full-chip physical design implementation. Candidate should have strong expertise in Floorpla

Job description Experience 5 years of hands-on experience in Identity and Access Management (IAM). Proven experience working with enterprise IAM platforms particularly Ping Identity solutions. Strong background in designing and implementing secure authentication and authori

Job description Experience 5 years of hands-on experience in Identity and Access Management (IAM). Proven experience working with enterprise IAM platforms particularly Ping Identity solutions. Strong background in designing and implementing secure authentication and authori

Job Title: STA Engineer PrimeTime Experience: 5 Years Location: Bangalore Job Description: We are looking for an experienced STA Engineer with 5 years of experience in Static Timing Analysis for complex SoC / ASIC designs. The ideal candidate should have strong hands-on e

Job Title: STA Engineer PrimeTime Experience: 5 Years Location: Bangalore Job Description: We are looking for an experienced STA Engineer with 5 years of experience in Static Timing Analysis for complex SoC / ASIC designs. The ideal candidate should have strong hands-on e

Job Title: DFT Engineer SCAN Experience: 5 Years Location: Chennai Job Description: We are looking for an experienced DFT Engineer with 5 years of experience in Scan DFT implementation and validation for complex SoC/ASIC designs. The ideal candidate should have strong han

Job Title: DFT Engineer SCAN Experience: 5 Years Location: Chennai Job Description: We are looking for an experienced DFT Engineer with 5 years of experience in Scan DFT implementation and validation for complex SoC/ASIC designs. The ideal candidate should have strong han

We are hiring for Role: Physical Design PNR Engineer Experience: 5 Years Location: Pune Job Description: * We are looking for an experienced Physical Design / PNR Engineer with 5 years of hands-on experience in block/full-chip physical design implementation. * Candidate should have

We are hiring for Role: Physical Design PNR Engineer Experience: 5 Years Location: Pune Job Description: * We are looking for an experienced Physical Design / PNR Engineer with 5 years of hands-on experience in block/full-chip physical design implementation. * Candidate should have

Job Title: Full Chip Physical Verification Engineer Experience: 5 Years Location: Chennai Job Description: We are looking for a Full Chip Physical Verification Engineer with 5 years of experience in Physical Verification (PV) for complex SoC / Full Chip designs. The candidate

Job Title: Full Chip Physical Verification Engineer Experience: 5 Years Location: Chennai Job Description: We are looking for a Full Chip Physical Verification Engineer with 5 years of experience in Physical Verification (PV) for complex SoC / Full Chip designs. The candidate

Job Title: Analog Layout Engineer Experience: 5 Years Location: Bangalore Job Description: We are looking for an experienced Analog Layout Engineer with 5 years of experience in custom/analog layout design. Candidate should have strong hands-on experience in TI (Texas Instrum

Job Title: Analog Layout Engineer Experience: 5 Years Location: Bangalore Job Description: We are looking for an experienced Analog Layout Engineer with 5 years of experience in custom/analog layout design. Candidate should have strong hands-on experience in TI (Texas Instrum

Role: PD PNR Engineer Experience: 5 Years Location: Pune Job Description: We are looking for an experienced Physical Design / PNR Engineer with 5 years of hands-on experience in block/full-chip physical design implementation. Candidate should have strong expertise in Floorpla

Role: PD PNR Engineer Experience: 5 Years Location: Pune Job Description: We are looking for an experienced Physical Design / PNR Engineer with 5 years of hands-on experience in block/full-chip physical design implementation. Candidate should have strong expertise in Floorpla

Job description Experience 5 years of hands-on experience in Identity and Access Management (IAM). Proven experience working with enterprise IAM platforms particularly Ping Identity solutions. Strong background in designing and implementing secure authentication and authori

Job description Experience 5 years of hands-on experience in Identity and Access Management (IAM). Proven experience working with enterprise IAM platforms particularly Ping Identity solutions. Strong background in designing and implementing secure authentication and authori

Job Title: STA Engineer PrimeTime Experience: 5 Years Location: Bangalore Job Description: We are looking for an experienced STA Engineer with 5 years of experience in Static Timing Analysis for complex SoC / ASIC designs. The ideal candidate should have strong hands-on e

Job Title: STA Engineer PrimeTime Experience: 5 Years Location: Bangalore Job Description: We are looking for an experienced STA Engineer with 5 years of experience in Static Timing Analysis for complex SoC / ASIC designs. The ideal candidate should have strong hands-on e

Job Title: DFT Engineer SCAN Experience: 5 Years Location: Chennai Job Description: We are looking for an experienced DFT Engineer with 5 years of experience in Scan DFT implementation and validation for complex SoC/ASIC designs. The ideal candidate should have strong han

Job Title: DFT Engineer SCAN Experience: 5 Years Location: Chennai Job Description: We are looking for an experienced DFT Engineer with 5 years of experience in Scan DFT implementation and validation for complex SoC/ASIC designs. The ideal candidate should have strong han