Lead Applications Engineer – DDR Design IP

At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.

The Cadence IP team develops industry leading IPs that enable customers in a variety of markets - from the endpoint to the edge to the cloud. At Cadence were helping set the standard on IP products that get integrated in SoCs that power the worlds Data Centers Automobiles Cloud and Wireless Systems. We offer amazing opportunities to grow no matter where you are in your career.

We are growing our Silicon Valley team and we are looking for smart energetic collaborative and creative people to help us lead the industry with our IP products. At Cadence we believe in embracing diverse ideas and striving for excellence in all that we do. Do you want to make a difference and be challenged Join the High-Performance Culture at Cadence.

As a Lead Technical Presales Engineer you will use your knowledge of different memory interface standards to architect memory solutions for customers using Cadence DDR IP.This role offers the benefit of both technical growth and business skill development. You will be part of the Technical Field Organization helping educate customers and providing solutions using our DDR IP portfolio. Our memory PHY and controller IPs are used in data centers mobile devices automobiles and consumer devices

Responsibilities include:

Technical presales of Memory IP

Present Cadences IP portfolio and capabilities to prospective customers

Work closely with IP Sales staff marketing and R&D teams to win opportunities

Performance evaluations of Cadence memory IP and development of related infrastructure

Serve as a product expert in memory controller and PHY IPs and protocols

Provide quick-turn product specific technical support to customers field teams definers and designers

Write application notes user guides articles design ideas new product proposals and evaluation kit manuscripts for internal and/or external publication

Travel to customer sites may be required occasionally

Qualifications:

BS in EE CE or related equivalent with 5 years of work experience or MS in EE CE or equivalent with 3 year of work experience

Knowledge of one or more DRAM protocols DDR4/5 LPDDR4/5/5X HBM2/3 GDDR6

Experience with simulation and synthesis tools

Strong knowledge of ASIC flow RTL/Verilog

Individual leadership and initiative to manage pre-sales accounts

Excellent presentation skills and verbal/written communication skills is a must

Nice to have:

Experience on memory subsystem verification and/or performance analysis

Knowledge of System Verilog and FPGA design

Knowledge of AXI DFI and MIPI protocols

Working knowledge of memory controller and memory PHY

The annual salary range for California is $102900 to $191100. You may also be eligible to receive incentive compensation: bonus equity and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications skill level competencies and work location. Our benefits programs include: paid vacation and paid holidays 401(k) plan with employer match employee stock purchase plan a variety of medical dental and vision plan options and more.

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