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Job Description:
Location preference: Bangalore
Work experience: 8 years
Develop verification plan by understanding requirement
Create constrained random verification ENV/ TB architecture usingSystem verilog & UVM
Exposed to Power aware simulation & GLS
Formal verification & Assertion will be added advantage.
Execute coverage plan & code cov closure.
Exposure to AMS verification
Experience in scripting languages like Perl Python.
DV candidate with experience in IP/ SOC/ SubSystem Verification and responsible to Develop verification plan by understanding requirement
Create constrained random verification ENV/ TB architecture using System verilog & UVM
Exposed to Power aware simulation & GLS
Formal verification & Assertion will be added advantage.
Execute coverage plan & code cov closure.
Experience in AMS verification
Experience in scripting languages like Perl Python.
Full Time