Staff SoC Physical Verification Engineer, HBM

Micron

Job Location:

Richardson, TX - USA

Monthly Salary: Not Disclosed

Posted on: 22 days ago

Vacancies: 1 Vacancy

Job Summary

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence inspiring the world to learn communicate and advance faster than ever.

As a Physical Verification Engineer you will be a key technical contributor within the Heterogeneous Integration Group (HIG) responsible for defining executing and driving sign-off quality physical verification flows for nextgeneration HBM logic die and memorycentric SoCs. You will work across physical design design rule development EDA tool teams foundry interfaces and product engineering teams to deliver industryleading tape-out-ready silicon under aggressive schedule quality and reliability constraints. This role combines full-chip physical verification ownership including DRC LVS ERC and DFM with deep collaboration across implementation and silicon bringup ensuring design integrity from layout through first silicon.

Responsibilities will include but are not limited to:

Lead endtoend physical verification signoff for fullchip and hierarchical designs including Design Rule Check (DRC) Layout Versus Schematic (LVS) Electrical Rule Check (ERC) Physical Electrical Rule Check (PERC) antenna checking and Design for Manufacturability (DFM).
Execute and debug foundryqualified rule decks manage waivers and drive clean closure while ensuring compliance with advancednode foundry requirements.
Perform reliability verification across multiple power domains including electrostatic discharge (ESD) latchup electromigration floating nets and connectivity checks.
Run density metal fill and chemical mechanical polishing (CMP) checks to ensure yieldaware manufacturability at 3 nanometer and below.
Perform parasitic resistancecapacitance (RC) extraction and support correlation of physical verification results with postsilicon measurements.
Develop maintain and optimize physical verification flows automation and regression infrastructure using Python Tcl Perl or similar scripting languages.
Drive adoption of machine learning (ML) and artificial intelligence (AI)based physical verification and powerperformancearea (PPA) optimization tools.
Partner with physical design custom layout computeraided design (CAD) registertransfer level (RTL) product engineering EDA and foundry teams including direct interface with TSMC from design kickoff through tapeout readiness and signoff decision gates.

Minimum Qualifications:

Strong experience with fullchip or blocklevel physical verification for advancednode systemonchip memory or heterogeneous integration designs.
Deep handson expertise in physical verification methodologies including DRC LVS ERC PERC DFM antenna and reliability signoff.
Experience using industry physical verification tools such as Calibre IC Validator (ICV) Pegasus or similar including rule deck development or customization.
Working knowledge of full RTLtoGDS implementation flows including placeandroute extraction and their impact on physical verification outcomes.
Ability to drive verification closure through strong crossfunctional communication in a global engineering environment.

Preferred Qualifications:

Experience with highbandwidth memory (HBM) DRAM or memorycentric systemonchip physical verification including multidie chiplet or 2.5D/3D integration.
Background in GPU CPU or highperformance accelerator physical implementation at advanced process nodes with aggressive signoff and tapeout schedules.
Familiarity with foundry design rule documents frontendofline (FEOL) and backendofline (BEOL) rules and advanced design for manufacturability best practices.
Exposure to postsilicon failure analysis yield learning or layoutbased debug with correlation between physical verification results and silicon behavior.
Masters or PhD in Electrical Engineering Computer Engineering or a related field or equivalent practical experience with 10 or more years of relevant industry experience including mentoring engineers and driving physical verification methodology improvements.

As a world leader in the semiconductor industry Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well provide peace of mind and help you prepare for the future. We offer a choice of medical dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury and paid family leave. Additionally Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available please see the Benefits Guide posted on is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race color religion sex sexual orientation age national origin citizenship status disability protected veteran status gender identity or any other factor protected by applicable federal state or local laws.

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Micron Prohibits the use of child labor and complies with all applicable laws rules regulations and other international and industry labor standards.

Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.

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Required Experience:

Staff IC

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence inspiring the world to learn communicate and advance faster than ever.A...