RTL2GDS, Senior Principal Design Engineer

At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.

The primary focus of Senior Principal Solutions Engineer is to support the adoption of Cadence Products to help Chip Designer Customers achieve superior performance for their Design PPA Goals. AEs are expected to possess Synthesis (logical and physical) Place and Route (primary focus) STA / SDC skills and some experience supporting tapeouts. Experience with multivoltage design implementation and clock tree debugging is desirable.

In addition Solutions Engineers are expected to be able to articulate design methodologies involving Cadence tools and be elevator talk proficient in the full Cadence tool portfolio. Development time will be spent gaining expertise in additional or specialization tools broadening focus from product emphasis to methodology Full Flow Implementation Training and learning to leverage success . Full Flow Services Projects involves owning block implementation top level implementation and Signoff focused efforts. Job exposure will be on RTL to GDSII delivery of projects. Theres an opportunity to get involved in competitive benchmarking on complex blocks including CPUs GPUs and DSP cores. These projects involve implementation in multiple technology nodes on standard foundry solutions. If you are looking to gain experience in methodology product delivery and working on cutting edge technology this is the right role for you.

Position Requirements:

* 7 years experience and a strong technical knowledge of company products.

* Design experience should include ASIC design using industry-standard hardware description languages (Verilog)

* Senior Level Applications Engineer position with Deep Cadence or Synopsys place and route tool knowledge (Physical Synthesis PnR CTS Static Timing Analysis) experience and knowledge are required

* Innovate with Low Power and Multi-Voltage Design Techniques working with leading edge Wireless and Mobile Customers

* Senior level Design Engineer position supporting RTL-to-GDS implementation flows using Encounter Digitial Implementation Platform

* Manage strategic customer evaluations/benchmarks on Cadences front-end solutions to establish technology differentiation and assert Cadence competitive advantages. Multiplex several issues and set priorities and exploit new technologies are essential for success in the position

* Assist customers with adopting Cadence Front End tools in Synthesis with Genus DFT & Scan with Encounter Test (ET) by providing methodology and tool knowledge to IC design process validated through successful design tapeouts

* Drive best practices and lessons learnt from evaluations/benchmarks and customer interactions back in to product development and Cadence field engineers. Develop an understanding of the customers needs and also of the competitions technology and sales strategies

* Support regional customers and support major level customer (50% plus support) in the local region

* Perform methodology assessments improve existing design methodologies and develop new ones that leverage Cadence technology and services.

* Assists sales staff in assessing potential application of company product to meet customer needs and preparing detailed product specifications.

* Create and conduct technical presentations and product demonstrations to customers

* Some TCL/Perl Scripting will be expected to achieve quick Design Automation solutions for customer

The Position Requirements are Normally requires a BS degree

NOT AN ENTRY LEVEL POSITION

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