Hardware & Silicon Validation Senior Principal Engineer

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.

At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.

Your Team Your Impact

What You Can Expect

Own and lead the overall validation strategy and execution for hardware platforms SoCs or subsystems from early bringup through production release.
Define validation architectures test plans and coverage metrics aligned to product requirements and standards (PCIe/PCI-SIG IEEE Ethernet JEDEC DDR).
Lead postsilicon bringup functional validation stress testing and cornercase validation across PVT conditions.
Lead board bring-up system integration link training and protocol validation (PCIe Ethernet DDR).
Own root-cause analysis and corrective action for complex cross-domain issues involving SoC PHY firmware and board.
Act as the technical point of contact for key customers through qualification deployment and post-FCS support.
Lead debug war rooms provide workarounds and deliver clear technical reports and best-practice guidelines.
Conduct customer trainings on protocols validation workflows and issue triage.
Partner with SoC/ASIC PHY Firmware/Software Diagnostics System Architecture Manufacturing/CM Program Management and Field/Apps.
Align validation plans and risk mitigation with program schedules quality objectives and customer commitments.

What Were Looking For

We are seeking a seasoned Hardware Validation Architect to lead end-to-end validation of complex systemsincluding functional electrical board-level production/qualification and customer engagementfor high-performance networking and compute platforms. The ideal candidate has deep hands-on expertise across PCIe Ethernet and DDR (DDR4/DDR5/LPDDR5) subsystems and thrives in cross-functional environments spanning silicon firmware system and manufacturing. This role is both technical and customer-facing responsible for defining strategy building validation frameworks ensuring quality at scale and guiding customers through deployment and issue resolution.

The candidate should have Bachelors degree in Computer Science Electrical Engineering or related fields and 15 years of related professional experience OR Masters / PhD degree in Computer Science Electrical Engineering or related fields with 10-12 years of experience.
Proven experience leading hardware or postsilicon validation efforts for complex SoCs ASICs boards or systems through multiple product cycles. Experience with production test development manufacturing qualification and failure analysis (FA/PA).
Handson expertise validating highspeed interfaces such as DDR (DDR4/DDR5) HBM PCIe Ethernet SerDes or similar technologies.
Solid understanding of SoC architecture hardwaresoftware interactions and systemlevel dependencies.
Experience validating designs against industry standards (JEDEC PCISIG IEEE etc.) and internal specifications.
Proficiency with lab equipment including oscilloscopes logic analyzers protocol analyzers traffic generators and power measurement tools.
Prior experience in customer-facing rolesfield support FAEs or validation leadership for enterprise customers.
Demonstrated ability to define and own endtoend validation strategy including test planning coverage definition execution and signoff criteria.
Excellent customer-facing communication: translating complex technical findings into clear actions for high-touch customers.
Communication excellence: concise lab reports executive-ready summaries and customer-facing documentation.

Expected Base Pay Range (USD)

The successful candidates starting base pay will be determined based on job-related skills experience qualifications work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .

Interview Integrity

To support fair and authentic hiring practices candidates are not permitted to use AI tools (such as transcription apps real-time answer generators like ChatGPT or Copilot or automated note-taking bots) during interviews.

These tools must not be used to record assist with or enhance responses in any way. Our interviews are designed to evaluate your individual experience thought process and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.