ASICS Electronics Engineer

Job Description

We are seeking an Electrical Engineer to support our work with the U.S. Army Research Laboratory (ARL) in Adelphi MD. The engineer will work with Application Specific Integrated Circuits (ASICS) and Field Programable Gate Arrays (FPGAs) and will work on-site in an integrated results-oriented research and development team environment within the Electronic Warfare (EW) Branch. We are seeking candidates to help develop innovative mixed-signal and photonics-Integrated Circuit (IC) solutions to support advanced Radio Frequency (RF) Machine Learning (ML) and signal-processing applications. Candidates should have strong hands-on experience with lab equipment FPGA front-end designs Application Specific Integrated Circuits (ASIC) and advanced node fabrication. You will work directly with senior technical personnel program managers and external organizations to help transition prototype systems to the U.S. Army development and acquisition enterprise.

HII has been providing engineering and management support to the U.S. Army Research Laboratory for over 20 years conducting innovative research to provide the Army with affordable enabling technologies in sensors EW quantum information sciences and ASICS technologies. We are seeking a candidate ready to explore these diverse technical areas within a state-of-the-art electronics research and development facility. Come be a part of this challenging and exciting opportunity!

Come support our work with the U.S. Army Research Laboratory and join a world class team of groundbreaking scientists and engineers!

Details below!

You will be part of a team that includes experts in ICs RF engineering and EW systems with direct support from HII engineers and industry recognized subject matter experts. Our team members are expected to have a basic understanding of RF FPGAs and ASIC technologies and be able to collaborate with various engineering and non-technical staff.

Essential Job Responsibilities

• Examine EW-relevant RF photonics ML and signal processing algorithms and propose innovations in the IC design space.
• Conceptualize mixed analog digital and photonics RF ML and signal processing algorithms and develop requirements and specifications.
• Predict performance using simulation methods such as PSpice FEKO Ansys SW.
• Identify specific design and simulation tools licenses and workflows needed to design and test mixed integrated circuits.
• Design mixed integrated circuits using tools such as Synopsys or Cadence design flows.
• Prototype front-end designs in high-performance FPGAs and demonstrate functional correctness.

Minimum Qualifications

• Recent graduate of PhD program from R1 university with experience in front-end design and functionality of FPGAs.
• Experience in laboratory RF hardware such as high-end oscilloscopes spectrum analyzers and anechoic chambers.
• Experience designing an ASIC using Synopsys or Cadence design flows including back-end design to include floor planning layout power rails clock trees and design-for-test.
• Experience implementing analog filters analog-to-digital converters digital-to analog converters and tuners in ASICs.
• Completed a GDSII.
• Strong communication (both written and verbal) skills.
• Ability to work independently and in a team environment.
• Ability to obtain a DoD/DoW security clearance.

Preferred Requirements

• Completion of Post Doc.
• Experience using fabrication service (MOSIS GF) and conducting verification.
• Completed mixed analog/digital design including non-standard logic cells.
• Completed integrated photonics digital and analog IC design.
• Experience in designing in 22 nm technology and below.
• Experience with front-end design of complex mathematical operators including Fast Fourier Transforms Convolutional Neural Networks and subspace operators (SVD PCA QR kernel transformations).