Design Verification Engineer Jobs in Santa Clara County, CA

About Marvell Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.At Marvell you can affect the arc of individual lives...

Sr Design Verification Engineer (Remote)Full-time: Salary Benefits Bonuses / ContractorWork Status: US citizen or Lawful Permanent Resident.Location: San Jose CA / RemoteAbout the Role:The ASIC Verification Engineer will play a crucial role in executing a comprehensive test strategy for future ASI...

About Marvell Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.At Marvell you can affect the arc of individual lives...

Your CareerAs a Design Verification engineer on the ASIC team you will ensure that the ASICs in our groundbreaking next-generation firewall products meet or exceed industry-leading requirements for features performance and reliability.  You will define verification methodologies architect test bench...

Your CareerAs a Design Verification engineer on the ASIC team you will ensure that the ASICs in our groundbreaking next-generation firewall products meet or exceed industry-leading requirements for features performance and reliability.  You will define verification methodologies architect test bench...

FPGA Verification Engineer Santa Clara CA 5days onsite Mandatory Areas Must Have Skills FPGA Verification Engineer Skill 1 8 Years of in FPGA Skill 2 5 Years of Exp in UVM Skill 2 5 Years of Exp in System Verlilog Job Description: We are seeking a highly motivated and skilled...

Title: FPGA Verification EngineerLocation: Santa Clara CA/On-SiteLong TermMandatory AreasMust Have Skills FPGA Verification EngineerSkill 1 8 Years of in FPGASkill 2 5 Years of Exp in UVMSkill 2 5 Years of Exp in System VerlilogGood To have SkillsSkill 1 Yrs of Exp N/ASkill 2 Yrs of Exp N/ASk...

Job Description:Minimum QualificationsTrack record of first-pass success in ASIC development cycles.Bachelors degree in computer science Computer Engineering relevant technical field or equivalent practical experience.8 to 10 years of hands-on experience in SystemVerilog/UVM methodologyExperience in...

Mandatory AreasMust Have Skills FPGA Verification EngineerSkill 1 8 Years of in FPGASkill 2 5 Years of Exp in UVMSkill 2 5 Years of Exp in System VerlilogLocation Santa Clara CAOnsite Requirement - Y/N- YNumber of days onsite 5 DaysIf Onsite Office Address Job Description:We are seeking a hi...