Principal Design Verification Engineer UAL & PCIe Subsystems

Principal Design Verification Engineer UAL & PCIe Subsystems

Location: Santa Clara CA
Work Arrangement: Onsite
Employment Type: Full-Time (Permanent)
Salary: $138000 $317800 per year

Vendor fee-10%
Net Pay- 90 days
Guarantee period-90days

About the Organization

Our client is a global leader in semiconductor and networking solutions developing high-performance chip architectures that power cloud computing telecommunications data centers and advanced computing systems.

The organization is recognized for its innovation in high-speed data transfer technologies and complex system-on-chip (SoC) designs. Its engineering teams work on cutting-edge solutions that enable scalable reliable and high-performance computing across a wide range of industries including enterprise telecom automotive and infrastructure.

With a strong engineering-driven culture the company emphasizes technical excellence collaboration and innovation in solving complex system-level challenges.

Position Overview

We are seeking a Principal Design Verification Engineer specializing in UAL and PCIe subsystems to join a high-impact verification engineering team.

In this role you will be responsible for architecting and developing advanced functional verification environments for high-speed interconnect and subsystem-level designs. You will work closely with design architecture and software teams to ensure correctness performance and compliance of complex SoC components.

This is a senior technical role requiring deep expertise in verification methodologies strong debugging skills and hands-on experience with PCIe or similar high-speed protocols.

Key Responsibilities Verification Planning & Strategy

• Develop detailed verification test plans using constrained-random and coverage-driven methodologies.

• Define functional coverage models and ensure completeness of verification scope.

• Collaborate with design and architecture teams to validate requirements and specifications.

Environment Development

• Architect and develop scalable verification environments using SystemVerilog and UVM.

• Build bus-functional models reference models monitors and drivers for subsystem verification.

• Develop reusable verification components for UAL and PCIe subsystems.

Test Development & Debugging

• Create directed and random test cases to validate design functionality.

• Execute simulation debug failures and work closely with design engineers to resolve issues.

• Perform root cause analysis for complex subsystem-level issues.

Protocol Verification (UAL / PCIe)

• Verify compliance and functionality of UAL and PCIe protocols at subsystem level.

• Develop and validate protocol-aware test scenarios.

• Work on performance data integrity and interface validation.

Tooling & Automation

• Develop tools and automation scripts using Python Perl or similar languages.

• Support regression testing and continuous verification workflows.

• Enhance verification efficiency through automation and scalable infrastructure development.

Software & System-Level Validation

• Verify boot code and support firmware/software integration testing.

• Contribute to development of scalable tools for multi-core and high-performance SoC environments.

• Support unit testing and regression validation of internal tools.

Collaboration & Leadership

• Work closely with cross-functional teams including design architecture and software engineering.

• Contribute to technical decision-making for verification strategies and methodologies.

• Operate independently while collaborating in a fast-paced development environment.

• Provide technical guidance and leadership on complex verification efforts.

Required Qualifications Education & Experience

• Bachelors Masters or PhD in Computer Science Electrical Engineering or Computer Engineering.

• 10 12 years of relevant experience in design verification.

Technical Skills

• Strong expertise in SystemVerilog and UVM.

• Experience building constrained-random coverage-driven verification environments.

• Strong understanding of functional coverage and test planning.

• Experience with scripting languages such as Python or Perl.

• Experience with EDA verification tools.

• Strong object-oriented design and programming skills.

Protocol Expertise

• Prior experience with PCIe protocol verification is required.

• Experience with UAL (or similar interconnect protocols) is highly preferred.

Additional Technical Skills

• Strong C programming skills.

• Good understanding of Linux operating systems.

• Exposure to ARM architecture or assembly is a plus.

Soft Skills

• Strong analytical and debugging abilities.

• Detail-oriented with strong ownership mindset.

• Ability to work independently with minimal supervision.

• Open to collaboration and differing technical opinions.

• Ability to learn quickly in a fast-paced engineering environment.

Compensation & Benefits

• Competitive salary range: $138000 $317800 annually

• Comprehensive health and wellness benefits

• Retirement and equity programs (as applicable)

• Opportunity to work on cutting-edge high-speed interconnect technologies

• Exposure to advanced SoC and subsystem-level design verification

• High-impact role in a global semiconductor engineering organization

Why Join

• Work on next-generation PCIe and high-speed interconnect technologies.

• Contribute to advanced subsystem verification for complex SoC platforms.

• Collaborate with world-class semiconductor engineering teams.

• High ownership role with technical leadership opportunities.

• Opportunity to work on scalable high-performance verification systems.