SeniorEngineer STPG Product Engineering Probe

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Job Description Summary

The Probe Product Engineer in STPG Product Engineering owns probe strategy and silicon learning at wafer test spanning presilicon designtoprobe staging firstsilicon bringup qualification and highvolume manufacturing (HVM).

This role is accountable for defining probe coverage intent establishing limits and guardbands grounded in silicon behavior and driving yield quality and testcost outcomes. The focus is on interpreting design intent device operation and process interactions and translating product risk into robust manufacturable probe strategies aligned with downstream test and customer requirements.

The engineer works closely with Design DFT Design Validation (DV) Process Integration Backend Test and Reliability teams to ensure probe solutions are technically sound scalable and productcentric across the lifecycle.

Career Growth & Impact

• Direct ownership of probe strategy and quality outcomes across the product lifecycle.
• Exposure to advanced technology nodes customerdriven requirements and largescale manufacturing systems.
• Clear growth paths across senior technical contributor product leadership or people management tracks within STPG Product Engineering.

Key Responsibilities

Probe Coverage Strategy & Ownership

• Define and own probe coverage intent by mapping design features device behavior and process risks into probe observability screening mechanisms trims and guardbands.
• Define release and sustain probe test flows from first silicon through qualification and HVM ensuring coverage objectives are met without unnecessary test overhead.
• Establish probe limits and guardbands based on silicon characterization design intent and customer specifications with clear alignment to downstream test.
• Lead probe enablement for new product introductions (NPI) and technology ramps identifying coverage and manufacturability risks early and driving mitigation plans.

PreSilicon DesigntoProbe Staging & DFT Readiness

• Partner with Design DFT and DV teams during presilicon phases to drive effective designtoprobe staging.
• Review and influence DFT architecture test hooks observability redundancy and trim structures to enable efficient and manufacturable probe coverage.
• Participate in presilicon verification and simulation reviews to reduce firstsilicon debug risk.
• Define probe coverage intent early and ensure continuity from design features through probe and downstream test (shiftleft learning).

First Silicon BringUp & Device Characterization

• Support firstsilicon bringup using engineering probe platforms and labbased characterization setups.
• Perform silicon and devicelevel characterization (parametric behavior margins trims stress response) to inform probe limits and screening strategy.
• Correlate early silicon behavior with probe results to validate coverage intent identify gaps and eliminate redundant content.
• Provide early silicon learning to accelerate probe flow stabilization and yield ramp.

Yield Quality & Reliability Enablement

• Drive waferlevel yield learning bin definitions and failuremode analysis at probe.
• Enable intrinsic and extrinsic screening strategies in collaboration with Reliability teams.
• Provide structured databacked feedback to Fab Process Integration Design and DV teams to close learning loops efficiently.

Test Efficiency & Cost Optimization

• Drive test efficiency improvements through coverage rightsizing and flow optimization aligned to product and market needs.
• Support waferlevel speed (WLS) activities as part of broader probe optimization efforts.
• Balance coverage yield quality and cost tradeoffs using silicon data and product risk understanding.

Data Analytics & AI Enablement

• Leverage probe inline and reliability data for yield analysis anomaly detection and decision support.
• Contribute to AI/ML initiatives such as predictive probe smart sampling and test optimization.
• Apply datadriven insights to continuously improve probe effectiveness and efficiency.

Artificial Intelligence

• Using applying and leveraging AI identify opportunities to streamline workflows optimize processes and support innovation by incorporating AI-driven solutions and enabling data-driven decision-making across projects and teams

Required Qualifications

• Bachelors Masters degree or Phd in Electrical / Electronics Engineering Computer Engineering (with strong hardware circuits or semiconductor focus) Semiconductor Physics or related field.
• Strong fundamentals in semiconductor devices wafer test and product engineering.
• Demonstrated ability to use silicon behavior and characterization data to make informed probe yield and coverage decisions.
• Experience or strong interest in silicon learning device behavior yield mechanisms DFT intent or designtomanufacturing integration.
• Strong analytical skills and ability to drive structured rootcause analysis.
• Effective communication skills and ability to work across global crossfunctional teams.

About Micron Technology Inc.

We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich lifefor all. With a relentless focus on our customers technology leadership and manufacturing and operational excellence Micron delivers a rich portfolio of high-performance DRAM NAND and NOR memory and storage products through our Micron and Crucial brands. Every day the innovations that our people create fuel the data economy enabling advances in artificial intelligence and 5G applications that unleash opportunities from the data center to the intelligent edge and across the client and mobile user experience.

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