SoC Mid Level Design Engineer (ARM Corestone)

SoC Mid Level Design Engineer (ARM / Corestone)

• Location: Hyderabad India
• Work Mode: Onsite (Full-time)
• Experience: 6 8 Years

We are looking for a SoC Design Engineer with experience in ARM-based subsystem design and integration. The role focuses on working with Arm Corestone reference systems and contributing to front-end ASIC design and RTL development.

You will collaborate with architecture verification and physical design teams to support integration debugging and delivery of SoC subsystems.

• Design and integrate ARM-based subsystems using Arm Corestone reference platforms
• Develop and modify RTL for CPU subsystems interconnects memory controllers and peripheral IP
• Work with architecture teams on feature definition and microarchitecture updates
• Integrate AMBA-based interconnects (AXI AHB APB) within SoC environments
• Collaborate with verification teams for debugging and functional coverage closure
• Support synthesis timing closure and backend implementation activities
• Perform Static Timing Analysis (STA) and assist in timing optimization
• Ensure design quality through lint CDC and RDC checks
• Participate in design reviews and maintain technical documentation
• Support FPGA prototyping emulation and early silicon bring-up
• Contribute to improvements in SoC integration methodologies and design flows

• Bachelors or Masters degree in Electrical Electronics or Computer Engineering
• 6 8 years of experience in SoC or ASIC front-end design
• Hands-on experience in RTL design and subsystem integration
• Strong understanding of ARM architecture and system-level design
• Experience working with Arm Corestone or similar ARM reference platforms

SoC / RTL Design:

• RTL design (Verilog/SystemVerilog)
• ASIC front-end design and integration flows
• CPU subsystem and IP integration

Architecture & Protocols:

• ARM architecture
• AMBA protocols: AXI AHB APB

Timing & Implementation:

• Static Timing Analysis (Primetime / Cadence tools)
• ASIC synthesis and timing closure

Verification & Signoff:

• CDC / RDC analysis (Spyglass or equivalent)
• Linting and functional debugging

Low Power & Tools:

• UPF-based low-power design (preferred)
• Power analysis tools (PowerArtist / Power Compiler optional)

Prototyping & Bring-up:

• FPGA prototyping (optional)
• Emulation and silicon bring-up (desirable)