Job Overview Duties include:
Module architecture and specification and helping with digital top architecture and specification.
Development of RTL using Verilog/System Verilog and doing block level testing before hand-off to verification.
Synthesis of RTL and doing quality analysis of netlist clock gating power gate count analysis gate level simulations LEC. Working with verification team in helping develop and review test plan for blocks and full device.
Perform Synthesis STA LEC and ATPG at digital core level.
Work with PnR/layout engineer to close placement CTS Utilization Timing for TO signoff.
Help with validation & bring-up related activities.
Exp in Logic design state machine
Exp in Project flow for digital synthesis net listing logic equivalence check
Ability to understand the block level specifications and arrive at appropriate architecture and design to meet those specifications.
Requirements
Experience in the range of 5 to 8 years.
A technology-related Bachelors degree with related experience.
Good engineering fundamentals.
Experience in RTL design from specifications
Basic understanding of one or more digital front-end tools : Synthesis STA LEC ATPG etc. Experience with these tools will be a plus.
Background in mixed-signal designs is a plus.
Ability to debug digital and mixed signal simulations would be a plus
Familiarity with post-silicon bench characterization in lab would be a plus.
Familiarity with asynchronous design would be a plus
Exposure to DC-DC converters would be a plus.
Excellent written and verbal presentation skills. Independent self starter
Required Skills:
Experience in the range of 5 to 8 years. A technology-related Bachelors degree with related experience. Good engineering fundamentals. Experience in RTL design from specifications Basic understanding of one or more digital front-end tools : Synthesis STA LEC ATPG etc. Experience with these tools will be a plus. Background in mixed-signal designs is a plus. Ability to debug digital and mixed signal simulations would be a plus Familiarity with post-silicon bench characterization in lab would be a plus. Familiarity with asynchronous design would be a plus Exposure to DC-DC converters would be a plus. Excellent written and verbal presentation skills. Independent self starter
Required Education:
Bachelors in Electronics or related field
Job Overview Duties include: Module architecture and specification and helping with digital top architecture and specification. Development of RTL using Verilog/System Verilog and doing block level testing before hand-off to verification. Synthesis of RTL and doing quality analysis of netlist ...
Job Overview Duties include:
Module architecture and specification and helping with digital top architecture and specification.
Development of RTL using Verilog/System Verilog and doing block level testing before hand-off to verification.
Synthesis of RTL and doing quality analysis of netlist clock gating power gate count analysis gate level simulations LEC. Working with verification team in helping develop and review test plan for blocks and full device.
Perform Synthesis STA LEC and ATPG at digital core level.
Work with PnR/layout engineer to close placement CTS Utilization Timing for TO signoff.
Help with validation & bring-up related activities.
Exp in Logic design state machine
Exp in Project flow for digital synthesis net listing logic equivalence check
Ability to understand the block level specifications and arrive at appropriate architecture and design to meet those specifications.
Requirements
Experience in the range of 5 to 8 years.
A technology-related Bachelors degree with related experience.
Good engineering fundamentals.
Experience in RTL design from specifications
Basic understanding of one or more digital front-end tools : Synthesis STA LEC ATPG etc. Experience with these tools will be a plus.
Background in mixed-signal designs is a plus.
Ability to debug digital and mixed signal simulations would be a plus
Familiarity with post-silicon bench characterization in lab would be a plus.
Familiarity with asynchronous design would be a plus
Exposure to DC-DC converters would be a plus.
Excellent written and verbal presentation skills. Independent self starter
Required Skills:
Experience in the range of 5 to 8 years. A technology-related Bachelors degree with related experience. Good engineering fundamentals. Experience in RTL design from specifications Basic understanding of one or more digital front-end tools : Synthesis STA LEC ATPG etc. Experience with these tools will be a plus. Background in mixed-signal designs is a plus. Ability to debug digital and mixed signal simulations would be a plus Familiarity with post-silicon bench characterization in lab would be a plus. Familiarity with asynchronous design would be a plus Exposure to DC-DC converters would be a plus. Excellent written and verbal presentation skills. Independent self starter
Required Education:
Bachelors in Electronics or related field
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Posted on:
4 hours ago
Vacancies:
1 Vacancy
