Senior Analog Mixed Signal DV Engineer

About TI
Texas Instruments Incorporated (TI) is a global semiconductor design and manufacturing company that develops analog ICs and embedded processors. By employing the worlds brightest minds TI creates innovations that shape the future of technology. TI is helping about 100000 customers transform the future today. Were committed to building a better future from the responsible manufacturing of our semiconductors to caring for our employees to giving back inside our communities and developing great minds. Put your talent to work with us change the world love your job!

Who are we and what do we do

The advanced circuits and power solution business is known for delivering industry leading custom IC system solutions including display and touch power products charger power products camera PMICs power path devices sensing devices and high-performance communication interface products. Our products integrate precision signal-chain and highly efficient power components in ultra-small form factors that enable TIs best-in-class customer to translate their ideas to high value products that revolutionize the personal electronics market.

In this team you will get to work with and learn from incredibly talented technical leaders who have influenced TI technology productivity and way of working in a creative and impactful way. You will get to directly interact with one of TIs valued and high-volume customers by way of intense technical reviews and architecture discussions!

By enabling designs that are highly impactful to TI revenue and working with a critical customer on a versatile set of products you will find yourself on an accelerated career path.

About the job

If you are looking to join an ingenious vigorous & ambitious team that consistently delivers groundbreaking technologies into the custom mobile electronics world here is an opportunity for you!

Senior Digital Design Verification (DV) Engineer

Location: Bangalore India

Experience: 510 Years

What will you be doing in this role

• Verification Strategy: Drive the verification strategy create detailed Test Plans with testcases checkers and coverage and develop comprehensive Test Benches for Chip Top levels.
• UVM Architecture: Responsible for grounds-up development of the DV environment including coding UVM components like agents drivers monitors and scoreboards.
• Full-Cycle Execution: Execute RTL and Gate Level Simulations (GLS) running regressions and tracking functional and code coverage (Block Expression Toggle FSM) to achieve 100% closure. Worked on standard communication protocols like I2C ASI SPI UART etc. Write assertions (SVA) coverages for verification completeness.
• Technical Debugging: Utilize excellent debugging and problem-solving skills to resolve complex design and testbench issues.
• Post-Silicon Support: Interact with Product and Application Engineering teams to support ATE functional pattern generation and silicon characterization.
• Cross-Functional Collaboration: Work closely with Architecture Design and Firmware teams to ensure successful product execution.

• Education: Bachelors or Masters degree in Electrical Engineering (EE) or Electronics and Communication Engineering.
• Experience: Minimum 5 years of experience in IP-level and SoC-level Digital Design Verification.
• Core Competencies: Strong expertise in SystemVerilog (SV) and UVM methodologies.
• Tools: Proficiency with Cadence simulation tools and environments (e.g. Xcelium Vmanager Jasper Gold).
• Communication: Effective communication and interpersonal skills to interact with worldwide cross-functional experts and stakeholders.
• Formal Verification (FV): Experience with Formal property verification (FPV) Connectivity checks and Unreachability (UNR) analysis for top-level sign-off.
• Clock & Reset Domain: Understanding of CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) assertions with the ability to write and debug them.
• Low Power Verification: Specific experience with UPF (Unified Power Format) for low-power verification and power-aware simulations.

• Automation Mindset: Ability to automate verification flows and repetitive tasks using Python Perl or Shell scripting.
• Mixed-Signal Exposure: Basic knowledge or exposure to AMS (Analog Mixed-Signal) verification environments is an added advantage.
• Methodology Innovation: Ability to innovate and drive improved verification methodologies and work with EDA teams to upgrade tools. Exposure to building AI-driven verification methodologies.