SoC Design Engineer – Junior Level (ASIC SoC)

Experience: 3 5 Years
Location: Bengaluru India
Employment Type: Full-time

B.E./ or M.E./ in Electronics Electrical Computer Engineering or a related discipline.

We are seeking a SoC Design Junior Engineer with hands-on experience in ARM-based SoC and subsystem design to support next-generation silicon development at Azimuth AI.

The ideal candidate will contribute to ARM Corestone based subsystem integration RTL development and front-end ASIC design working closely with architecture verification and physical design teams to deliver production-quality SoCs.

• Design and integrate ARM-based subsystems derived from Arm Corestone reference systems into complex SoCs

• Develop modify and integrate RTL (Verilog/SystemVerilog) for CPU subsystems AMBA interconnects memory controllers and peripheral IPs

• Collaborate with architecture teams on micro-architecture updates feature definition and performance goals

• Work closely with verification teams to debug functional issues and achieve coverage closure

• Support synthesis STA CDC/RDC and handoff to physical design teams

• Participate in design reviews documentation and subsystem bring-up for simulation emulation FPGA and early silicon

• Contribute to methodology improvements for scalable subsystem integration and reuse

• Bachelors or Masters degree in Electronics Electrical or Computer Engineering

• 3 5 years of hands-on experience in SoC or subsystem RTL design

• Strong understanding of ARM architecture and AMBA protocols (AXI AHB APB)

• Practical experience with Arm Corestone reference designs or equivalent ARM-based subsystems

• Solid background in ASIC front-end design flows (RTL development & integration)

• Experience with Static Timing Analysis (PrimeTime / Cadence tools)

• Hands-on exposure to CDC/RDC linting and synthesis flows (SpyGlass or equivalent)

• Strong debugging skills across simulation lint CDC and synthesis environments

• Ability to work effectively in a cross-functional fast-paced engineering environment

• Exposure to low-power design techniques UPF and power-aware design flows

• Familiarity with PowerArtist Power Compiler or equivalent tools

• Experience with FPGA prototyping emulation platforms or silicon bring-up

• Exposure to AI/ML accelerator-based SoCs is a strong plus

• Work on cutting-edge ARM-based SoCs for AI-driven platforms

• Learn and grow across architecture RTL and subsystem integration

• Collaborate with experienced silicon architects and domain experts

• Strong technical ownership with clear growth toward Senior SoC Design roles

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