Design Verification Manager
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Job Location:
Monthly Salary:
Posted on:
5 hours ago
Vacancies:
1 Vacancy
Job Summary
About the Role
Senior technical leadership position responsible for ASIC/RTL design verification team management and implementation of verification strategies using advanced tools and methodologies.
Key Responsibilities
- Lead and manage verification team of 10 members (Must have)
- Develop and implement verification strategies using System Verilog
- Oversee OVM/UVM implementation and verification processes
- Manage simulation environments across multiple platforms
(Synopsys/Mentor Graphics/Cadence) - Drive scripting and automation initiatives
- Lead debugging and analysis of complex digital design issues
- Oversee verification of processor subsystems
- Manage validation suite creation and automation
- Guide silicon bring up and testing processes
- Ensure quality and completeness of verification deliverables
Qualifications & Skills
- B.E/ in Electrical/Electronic Engineering
- 10 years in ASIC/RTL design verification
- System Verilog Testbench Architecture OVM UVM expertise Simulator
tools (Synopsys/Mentor Graphics/Cadence) - Scripting languages (Perl Python Shell Tcl/Tk) Hardware verification languages (SystemVerilog
SystemC) Hardware description languages (Verilog VHDL) AMBA AHB AXI - JTAG protocols Gate-Level Simulation and Debugging
Processor subsystems (ARM/RISC) Silicon testing and bench
application.
Key Skills
- Arabic Speaking
- Logistics Operations
- Lecturing
- Community Support
- Gynaecology & Obstetrics
- AC Maintenance
