Staff Digital Verification Engineer

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the worlds most highly integrated SoCs Silicon Labs provides device makers the solutions support and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin Texas Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home industrial IoT and smart cities markets. Learn more at.

Staff Digital Verification Engineer
Austin TX

About the team
The IoT Digital Design team is a state-of-art IC design team focused on producing world class Wireless MCU SoCs. The architecture specification design verification emulation and implementation of the Wireless MCU SoCs is the responsibility of the IoT Digital team. These SoCs include an embedded CPU system with analog and digital peripherals advanced security advanced power management and best in class radios to support a wide range of wireless IoT applications and standards. We strive to provide best in class technology solutions through innovation in custom RISC-V Cores and AI/ML components.

Responsibilities

• Block and IP Verification
  • Block level verification to validate block performance and adherence to requirements.
  • Generate and execute verification plan based on specifications.
  • Architect and implement testbenches and verification components using UVM-based methods.
  • Coverage definition implementation and analysis.
  • Architect and Implement Formal Verification solutions.
  • Mixed-signal IP integration including real-number modeling.
• DSP and Communication
  • Verify block and subsystem testbenches related to wireless protocols.
  • Use MATLAB models for data path verification.
  • Debug functional issues in PHY and MAC layer.
• Flows and Methodology
  • Identify and develop verification flows and methodologies to enhance IP SoC Mixed Signal or Formal Verification.

Minimum Qualifications

• Bachelor or masters degree in electrical and/or Computer Engineering

• 8 years of design experience.
• Industry experience developing testbenches and verification components with SystemVerilog and UVM is required.
• Technical leadership and mentoring experience.
• Knowledge of scripting/language (Python PERL shell TCL).
• Design/Verification skills
  • Software/Firmware coding (C)
  • SystemVerilog Assertion and coverage analysis
  • Low-power implementation (UPF)
  • Mixed Signal Real Number Modeling (RNM Spice)
• Experience with artificial intelligence (AI) powered tools and technologies used to enhance productivity analysis and decision-making

The following qualifications will be considered a plus

• Mixed Signal verification with RNM and SPICEmodels
• DSP digital wireless modulation schemes FEC
• Verification and debug of low-power designwith UPF
• Mentoring skills.
• Exceptional problem-solving skills.
• Good written and oral communication skills.
  

Benefits & Perks

You can look forward to the following benefits:

• Great medical (Choice of PPO or Consumer Driven Health Plan with HSA) dental and vision plans
• Highly competitive salary
• 401k plan with match and Roth plan option
• Equity rewards (RSUs)
• Employee Stock Purchase Plan (ESPP)
• Life/AD&D and disability coverage
• Flexible spending accounts
• Adoption assistance
• Back-Up childcare
• Additional benefit options (Commuter benefits Legal benefits Pet insurance)
• Flexible PTO schedule
• 3 paid volunteer days per year
• Charitable contribution match
• Tuition reimbursement
• Free downtown parking
• Onsite gym
• Monthly wellness offerings
• Free snacks
• Monthly company updates with our CEO

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Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race religion color national origin gender sexual orientation age marital status veteran status or disability status or any other characteristic protected by applicable law.