PCIe Verification Engineer
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Job Location:
San Jose, CA - USA
Monthly Salary:
Not Disclosed
Posted on:
19 hours ago
Vacancies:
1 Vacancy
Job Summary
Role: PCIe Verification Engineer
Rate: Market rate - Submit at the best rate.
Position Type: Contract
Location: San Jose CA Or Silver Lake CO.
Job Description:
Experience: 7 Years Education: Bachelor/Master of Engineering (B.E./ in Electronics Electrical Computer Engineering or a related field
Role Summary:Drive the pre-silicon verification of next-generation PCIe Switch and Retimer designs across Gen4 Gen5 and Gen6 specifications. Utilizing SystemVerilog and UVM you will ensure robust protocol compliance high-performance throughput and seamless interoperability for cutting-edge silicon.
Key Responsibilities:- Strategic Planning: Architect and execute comprehensive PCIe verification plans to ensure full specification coverage.
- Environment Development: Build and maintain sophisticated UVM-based verification environments from the ground up.
- Protocol Deep-Dive: Verify intricate PCIe protocol behaviors including LTSSM transitions link training flows and complex error handling mechanisms.
- Feature Validation: Validate specialized Switch and Retimer features alongside cross-vendor interoperability.
- RTL Debugging: Perform rigorous debug of RTL and protocol-level issues while conducting detailed functional and code coverage analysis.
- Protocol Expertise: Strong command of PCIe protocols specifically Gen4 and Gen5 with Gen6 knowledge considered a significant advantage.
- Methodology: Advanced proficiency in SystemVerilog UVM and the implementation of functional assertions.
- Tooling: Extensive experience navigating industry-standard simulators such as VCS Questa or Xcelium.
- Compliance & Physical Layer: Familiarity with PCI-SIG compliance testing SerDes/Signal Integrity (SI) fundamentals and hardware emulation environments.
Key Skills
- Account Management
- Apache Web Server
- Jpa
- ABAP
- Community Support
- Islamic Banking
