TITILE: RTL DESIGN ENGINEER (Principal/Senior Staff/Staff Engineer)
Location: Bangalore/Hyderabad
EXPERIENCE: 10 years to 15 years
RTL design in Verilog/SystemVerilog
-Micro-architecture integration & debug
-Synthesis-friendly coding practices
-Experience in ASIC SoC designs
ROLES AND RESPONSIBILITIES:
-RTL design in Verilog/SystemVerilog
-Micro-architecture integration & debug
-Synthesis-friendly coding practices
-Experience in ASIC SoC designs
TITILE: RTL DESIGN ENGINEER (Principal/Senior Staff/Staff Engineer) Location: Bangalore/Hyderabad EXPERIENCE: 10 years to 15 years RTL design in Verilog/SystemVerilog -Micro-architecture integration & debug -Synthesis-friendly coding practices -Experience in ASIC SoC designs ROLES...
TITILE: RTL DESIGN ENGINEER (Principal/Senior Staff/Staff Engineer)
Location: Bangalore/Hyderabad
EXPERIENCE: 10 years to 15 years
RTL design in Verilog/SystemVerilog
-Micro-architecture integration & debug
-Synthesis-friendly coding practices
-Experience in ASIC SoC designs
ROLES AND RESPONSIBILITIES:
-RTL design in Verilog/SystemVerilog
-Micro-architecture integration & debug
-Synthesis-friendly coding practices
-Experience in ASIC SoC designs
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