About :
Wipro is a global IT consulting and business process services company that helps businesses with digital transformation offering services in cloud computing AI analytics cybersecurity and software engineering to modernize operations and build intelligent sustainable solutions for various industries.
ASIC RTL
Mandatory Skill :
(RTL Design RTL Coding & Integration RTL quality checks (Lint CDC) IP targeted for SOC Static checks Protocols - PCIe DDR EthernetI2C UART SPI)
Experience :
6 Years 22 Years
JD:
Expertise in SoC subsystem/IP design
Expertise in IP design Subsystem/Cluster and SoC level integration using Verilog/System Verilog
In depth knowledge on RTL quality checks (Lint CDC)
Knowledge of synthesis and low power is a plus
Good understanding of AMBA bus protocols (AXI AHB ATB APB)
Good understanding of timing concepts
Knowledge of one or more of the interface protocols
a. PCIe
b. DDR
c. Ethernet
d. I2C UART SPI
Expertise in setting up and using tools like
a. Spyglass Lint/CDC
b. Synopsys DC
c. Verdi/Xcellium
Understanding of scripting languages like Make flow Perl shell python etc
Understanding of processor architecture and/or ARM debug architecture is a plus
Able to help and debug issues for multiple subsystems
Able to create/review design documents for multiple subsystems
Able to support physical design verification DFT and SW teams on design queries and reviews
About : Wipro is a global IT consulting and business process services company that helps businesses with digital transformation offering services in cloud computing AI analytics cybersecurity and software engineering to modernize operations and build intelligent sustainable solutions for various...
About :
Wipro is a global IT consulting and business process services company that helps businesses with digital transformation offering services in cloud computing AI analytics cybersecurity and software engineering to modernize operations and build intelligent sustainable solutions for various industries.
ASIC RTL
Mandatory Skill :
(RTL Design RTL Coding & Integration RTL quality checks (Lint CDC) IP targeted for SOC Static checks Protocols - PCIe DDR EthernetI2C UART SPI)
Experience :
6 Years 22 Years
JD:
Expertise in SoC subsystem/IP design
Expertise in IP design Subsystem/Cluster and SoC level integration using Verilog/System Verilog
In depth knowledge on RTL quality checks (Lint CDC)
Knowledge of synthesis and low power is a plus
Good understanding of AMBA bus protocols (AXI AHB ATB APB)
Good understanding of timing concepts
Knowledge of one or more of the interface protocols
a. PCIe
b. DDR
c. Ethernet
d. I2C UART SPI
Expertise in setting up and using tools like
a. Spyglass Lint/CDC
b. Synopsys DC
c. Verdi/Xcellium
Understanding of scripting languages like Make flow Perl shell python etc
Understanding of processor architecture and/or ARM debug architecture is a plus
Able to help and debug issues for multiple subsystems
Able to create/review design documents for multiple subsystems
Able to support physical design verification DFT and SW teams on design queries and reviews
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