ASIC Design Engineer
Share
Job Location:
Monthly Salary:
Posted on:
4 days ago
Vacancies:
1 Vacancy
Job Summary
KEY RESPONSIBILITIES
- Help develop the design and implementation of SoCs.
- Micro-architecture design RTL coding synthesis timing closure and documentation of various RTL blocks;
- Top-level and block-level performance bandwidth and power optimization;
- Work with FPGA engineers to perform early prototyping; and
- Support test program development chip validation and chip life until production maturity.
- Collaboration with firmware software DV FPGA DFT SoC integration and backend teams throughout various stages of ASIC development.
Qualifications
- 8 years of experience in RTL logic design verification synthesis and timing optimization;
- Proficient in writing clear implementable micro-architecture specifications;
- Expertise in writing efficient RTL code in Verilog and SoC integration
- Good understanding of assertions coverage analysis RTL synthesis and timing closure;
- Should have worked on interface protocols like PCIe USB Ethernet DDR3/4 LPDDR I2C/I3C SPI SD/SDIO/eMMC UART etc.
- Experience in design bring up and debug on FPGA based emulation platforms like HAPS Veloce.
- Fluency with scripting languages (e.g. Perl Python);
- Must have gone through at least one tapeout.
- Preferred: Silicon bring-up and debug experience
- Experience in working with repository management tools like Bitbucket/ Jenkins and bug tracking tools like JIRA.
Key Skills
- Mechanical Design
- SOC
- System Design
- GD&T
- CAD
- Creo
- SolidWorks
- Mechanical Engineering
- Perl
- Autocad
- HVAC Design
- Catia
