Analog IC Design Engineer,

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.

At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.

Your Team Your Impact

What You Can Expect

Seeking a Senior Analog IC Designer to be part of a Marvells central engineering team designing highly sophisticated CMOS LR SERDES D2D and common Analog IPs. Responsibilities would span architectural investigations and implementation for circuits such as PLL DLL ADC regulators amplifiers TX RX CDRs etc. to meet key performance targets and performing design verification using industry standard tools such as SPICE Spectre MATLAB etc.

In this role successful candidate will lead a team of analog design engineers interface with layout verification and application teams and manage delivery of analog IP to successfully bring designs from concept to production.

What Were Looking For

Masters degree and/or PhD Preferred in Electrical Engineering or related fields with 8 years of experience. A successful candidate should have experience in some of the following designs:

D2D IP PLL Data Converters Oscillators and high-speed SerDes design including Receiver and Transmitter design.

Experience with 112G SerDes speed especially short reach and low power designs

Experience in Single-ended High Density Parallel Interface for Chip to Chip Communication UCIe DDR5/LPDDR5; GDDR6/LPDDR6 a plus

Experience with analog design and verification tools (Virtuoso Spectre ADE and post layout extraction tools) is a must

Knowledge of the fundamentals on signal integrity improvement noise reduction and Multi-GHz low-jitter clock generation & distribution.

Good understanding of analog layouts in FinFet and its effect on high-speed designs

Experienced in system level pre-tape out analog validation

Experienced in lab chip bring-up and debugging efforts

Strong communication skills

Additional Compensation and Benefit Elements

With competitive compensation and great benefits you will enjoy our workstyle within an environment of shared collaboration transparency and inclusivity. Were dedicated to giving our people the tools and resources they need to succeed in doing work that matters and to grow and develop with us. For additional information on what its like to work at Marvell visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Interview Integrity

To support fair and authentic hiring practices candidates are not permitted to use AI tools (such as transcription apps real-time answer generators like ChatGPT or Copilot or automated note-taking bots) during interviews.

These tools must not be used to record assist with or enhance responses in any way. Our interviews are designed to evaluate your individual experience thought process and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.