Design Verification Engineer, SSG

As a Design Verification (DV) Engineer you will be part of an advanced architecture team that is exploring new hardware designs to improve our this role you will be responsible for defining the verification methodology and implementing the corresponding test plan for advanced functional blocks. You will participate in the design verification and bring-up of such blocks by writing relevant assertions debugging code test benches test harnesses and otherwise interacting with the extended team. You will participate in the lab bring-up of these blocks either in an FPGA or silicon by potentially writing test scripts analyzing lab data proposing experiments etc.

You will work closely with multi-disciplinary groups including Product Design Audio Technology Computer Vision Hardware Engineering and Software Engineering to architect and implement complex functional block that enable development of world-class hardware devices.

In this role you will:
Design world class hardware and software
Communicate and work with team members across multiple disciplines
Deliver detailed test plans for verification of complex digital design blocks by working with design engineers and architects
Create and enhance constrained-random verification environments using SystemVerilog and UVM
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.
Participate in test plan and coverage reviews

The ideal candidate should have experience with RTL development environments fluency in modern hardware description languages and verification methodologies. They should have experience verifying complex IP blocks from scratch that have successfully been integrated in SOCs or other such silicon that have been productized in consumer devices. We are looking for a self-driven individual who can work with architects HW and SW developers and can quickly resolve blocking issues.




- Bachelors degree in Electrical Engineering or a related field
- Experience developing high quality test plans test designs test strategies and test execution
- Experience identifying bugs in architecture algorithms functionality and performance with strong overall debugging skills
- Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing
- Experience with industry standard tools and scripting languages (Python or Perl) for automation
- Experience in English-language communication skills both written and verbal
- Experience using multiple verification platforms: UVM test bench FPGA emulator software environments and system testing
- Experience with test plan development building the necessary test bench infrastructure developing tests and verifying the design
- 4 years or more of practical semiconductor design verification including System Verilog UVM assertions and coverage driven verification.

- Masters degree in Electrical or Communications Engineering or a related field
- Experience in system-level debugging
- Experience working with high-performance industry standard buses like AMBA AXI4
- Experience with formal verification techniques including abstraction and end-to-end checking
- Experience with embedded software
- Knowledge of SoC architecture
- Experience with CPU block level testing.
- Strong programming skills in C/C and scripting skills in Python and/or Perl.
- Experience with transaction level modeling.
- Knowledge of FPGA and emulation platforms.

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