Staff Hardware Security Engineer

The SoC Architecture team is responsible for defining high-performance and power efficient System-on-Chip hardware architecture.

The team identifies Hardware Requirements defines the overall SoC system and delivers High-level Architecture Specification (HAS) integrating multiple processing units memory interconnects accelerators interfaces and peripherals to achieve optimal Power Performance Area and Cost (PPAC) efficiency. The team is also responsible for overall aspects of security debug production test and device packaging and for defining and maintaining Configuration Management processes for scalable and configurable architectures.

The team works closely with Product Technology Software and AI and Hardware Engineering Teams for Design Implementation and Verification.

The Role:

You will be responsible for all aspects of Hardware Security throughout the Concept Definition and Specification of Hardware this team your responsibility will include but not limited to:

• Architect and define overall SoC including processing units hardware accelerators memory interconnect interfaces and analog components.
• Work hand in hand with the product architects making sure hardware architecture meets the product goals.
• Support the implementation of Security features and the intersection of security features with all aspects of Hardware Architecture and Design and Software implementation.
• The development of hardware architecture security models involves mapping reference models and adversarial models while also addressing the security objectives of the ecosystem.
• Security considerations encompass a range of elements including but not limited to the identification of assets mapping use cases and threats and the development of a Trusted Computing Base (TCB) with a Root of Trust(RoT). Key aspects also include secure boot processes data protection measures isolation and attestation solutions detection of data compromises and the integration of security features and intellectual properties (IPs).
• Conduct system-level modelling and analysis to optimise for power performance area and cost.
• Evaluate new processes technologies trends and industry standards.
• Perform hard and soft IP identification analysis and selection.
• Lead architecture definition reviews and provide technical guidance.
• Work with peer micro architect across the organization aligning product and architecture definition.
• Collaborate with design implementation verification physical design software and firmware teams for development and design convergence.
• Support SoC execution across project milestones working with all cross functional teams to identify and drive complex dependencies resolution.
• Define and develop system-level methodologies tools and IPs to build SoCs in an efficient and scalable manner.
• This role requires a talent for cross-functional collaboration where effective communication and engagement are essential throughout the entire Product Development process with a strong emphasis on security.

Qualifications:

• Bachelors Masters or PhD in Electrical Engineering Computer Engineering or related field
• 10 years of solid experience in IP/SoC architecture and design for ASIC or FPGA

Skills and Knowledge:

Foundational understanding and familiarity with key security themes is desired including:

• Confidential Computing: Concepts such as memory separation and encryption in hardware exemplified by technologies like Intel TDX AMD SEV RISC-V CoVE and confidential containers.
• Memory Separation for Trusted Applications: Technologies including Intel SGX ARM Trust Zone and RISC-V PMP/Keystone.
• Cryptographic Intellectual Properties (IPs): Knowledge of hash functions (SHA1/2/3) symmetric cryptography (AES ChaCha20)asymmetric/PKI cryptography (RSA ECDSA EdDSA) HMAC and AEAD.
• Usage of Crypto Libraries with Hardware Crypto IPs: Familiarity with libraries such as OpenSSL libssl wolfSSL mbedTLS and libsodium particularly in relation to SHA2 HMAC Poly1305 AES ChaCha20AEAD RSA ECDSA and EdDSA.
• Secure Boot: Understanding boot binary verification hash validation signature variations encryption/decryption processes certificate creation and usage and the role of TPM.
• Remote and Local Attestation Use Cases: Insights into Over-The-Air(OTA) updates and JTAG security.
• Experience with architecture trade-offs and design methodologies for optimal performance power area cost (PPAC) in advanced technologies.
• Proficiency in performance modelling simulation frameworks and scripting.
• Strong knowledge and industry expertise in multiple aspects of SoC architecture definition such as Clocks Resets Power-Sequencing Power Management Interrupts Interconnects Boot Virtualization Security System Performance IO technologies Platform integration.
• Experience with RISC-V based Systems.
• General knowledge with industry standard integration tools.
• General knowledge of SoC implementation standards interconnect (AMBA AXI CHI) and interfaces (PCIe UCIe I2C I3C SPI JTAG).
• General knowledge of Advanced packaging (2.5D 3D SiP CoWoS) and chiplets.

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