Design Engineering Architect
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Job Summary
At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.
Responsibilities
- Manage a team of verification engineers for interconnect IP. Also required to pitch in with the technical contributions as required.
- Relevant experience in interconnect and subsystems is strongly preferred
- Crafting and reviewing verification plan. Manage the overall execution on those plans to verify highly complex and configurable designs.
- Responsible for verification closure and sign off.
- Work closely with cross functional teams (DV/Arch/Design/PD/GUI).
- Identify and hire talent to grow the team as needed.
Required Skills and Experience:
- 15 years of design verification experience
- BS (or higher) in EE/Computer Engineering
- Experience in managing a team of 5 engineers.
- Experience in hiring and building the team training and developing engineers.
- Strong interpersonal skills. Excellent at identifying and communicating requirements delegating tasks.
- Excellent knowledge of Interconnects NoCs and design verification fundamentals.
- Thorough understanding of System Verilog UVM and other programming languages to build flexible and reusable complex testbenches.
- Strong technical skills to review the code make constructive suggestions and overall ability to maintain the codebase to avoid future technical debt.
- Experience with development of fully automated flows manage regression cycles and monitor coverage progression.
- Exposure to scripting languages like Perl Unix shell or similar languages would be a plus.
Were doing work that matters. Help us solve what others cant.
Key Skills
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About Company
Do you want to shape the future of technology? Cadence is leading the charge to solve some of technology’s toughest challenges. We work with the world’s most innovative companies, across a growing range of industries. Major trends that you hear about everyday – like artificial intell ... View more
