Sr. Staff Timing Engineer

Toronto - Canada

Monthly Salary: Not Disclosed

Posted on: 28 days ago

Vacancies: 1 Vacancy

Job Summary

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI automotive and carrier architectures our innovative technology is enabling new possibilities.

At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.

Your Team Your Impact

Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products.

What You Can Expect

ASIC design engineer responsible for post RTL design flow. He/She will be responsible for block and /or chip level synthesis timing closure DFT generation and ECOs.

The responsibilities include but not limited to.

Improve the design methodology and flow.
Synthesis timing closure and DFT support for various type of SerDes IPs ranging from 10Gbps to 224Gbps data-rates for different applications.
Collaborate with Analog/Digital design teams to deliver the competitive SerDes IP solutions for all the Marvell product lines.
Provide the support to the product teams for both pre and post silicon

What Were Looking For

Bachelors degree in Computer Science Electrical Engineering or related fields and 6 years of related professional experience.

Masters degree and/or PhD in Computer Science Electrical Engineering or related fields with 4 years of experience.

Good personal communication skills and team working spirit.

Hardworking and motivated to be part of a highly competent design team.

Must have good post-RTL experience including synthesis timing analysis and physical design. Able to perform custom placement and routing for mixed-signal designs. Flexible to move between all post-RTL design activities as required. Good understanding of block and top-level physical timing closure.

Must be proficient in the following skills:

Logic or physical synthesis using Synopsys or Cadence tools
Static timing analysis using Primetime
Physical design for 28nm and beyond
DFT generation and verification
Strong Perl and Tcl scripting skill

Highly desirable skills:

Low power design
IR drop analysis
Circuit level or custom design experience
Floorplanning clock-tree synthesis and power planning/analysis
Signal integrity and physical verification
PnR flow development

Additional Compensation and Benefit Elements

With competitive compensation and great benefits you will enjoy our workstyle within an environment of shared collaboration transparency and inclusivity. Were dedicated to giving our people the tools and resources they need to succeed in doing work that matters and to grow and develop with us. For additional information on what its like to work at Marvell visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Interview Integrity

As part of our commitment to fair and authentic hiring practices we ask that candidates do not use AI tools (e.g. transcription apps real-time answer generators like ChatGPT CoPilot or note-taking bots) during interviews.

Our interviews are designed to assess your personal experience thought process and communication skills in real-time. If a candidate uses such tools during an interview they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.

#LI-TD1

Required Experience:

Staff IC

About MarvellMarvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI automotive and carrier architectures our innovative technology is enabling new possibilities.At Marvell you can affect the arc of individ...