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You will be updated with latest job alerts via email2-3years
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Salary Not Disclosed
1 Vacancy
ACG2741JOB
Our client is a leading semiconductor manufacturing company who is looking for a qualified candidate to join their firm.
Contribute to the architecture and RTL design of IP blocks and full SoClevel integration.
Design and configure CPU subsystems within ARMbased systemonchip platforms.
Generate and manage IP configurations particularly for core system components.
Design and customize highspeed interface IPs (e.g. PCIe) and generalpurpose peripherals (e.g. DMA).
Integrate IPs at chip and block level using IPXACT methodologies.
Conduct verification tasks including simulation linting clock domain crossing (CDC) and designfortest (DFT) checks.
Support physical design efforts including scripting for timing constraints (SDC).
Minimum 2 years of handson experience in RTL design particularly for IP or SoC development.
Solid foundation in computer architecture Verilog and SystemVerilog.
Nice to Have:
Familiarity with highspeed interfaces such as PCIe.
Experience working with systemlevel IPs like processors cache systems SoC interconnects and DRAM controllers.
Understanding of compute accelerators including NPUs GPUs and Large Language Model Accelerators (LLMAs).
Exposure to power optimization techniques in chip design.
Preferred Attributes:
Works effectively with crossfunctional teams to identify root causes and resolve technical challenges.
Capable of balanced and thoughtful decisionmaking within a collaborative environment.
Strong communicator with the ability to coordinate closely with teams across borders especially in Korea.
Contact: Giang Tran or Giau Nguyen
Due to the immense number of applications only shortlisted candidates will be contacted.
Full Time