Wireless SOC Design Verification Engineer
Wireless SOC Design Verification Engineer
Posted on :
04-08-2025
Employer Active
1 Vacancy
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Monthly Salary
USD 171600 - 302200
Vacancy
1 Vacancy
Posted on :
04-08-2025
Job Description
Understand details of High Efficiency SOC Architecture standard SOC peripherals such as PCIE Power Management & Low-Power schemes DMA CPUs and multi-processor systems DDR PCIe Memory Controller Subsystems USB PLL power up Secured Boot schemes. Deliver on Power Management designs using low-power methodologies and power up-down scenarios using UPF coverage driven verification plans from specifications review and refine to achieve coverage targets. Architect UVM based highly reusable test benches and integrate complex multi-instance VIPs sub-system test benches and test suites to SOC targeted coverage work with design architecture SW FW and external IP delivery teams to efficiently integrate and verify overall SOC closely with DV methodology architects to improve verification metrics.
- BS and a minimum of 10 years relevant industry experience.
- Dedicated/hands-on ASIC & SOC DV experience.
- Sophisticated knowledge of HVL methodology (UVM/OVM) with most recent experience in UVM.
- Experience with formal verification is a plus.
- Proven track record of working full ASIC cycle from concept to tape-out to bring-up including test-planning testbench implementation test sequence creation and debugging and coverage closure.
- Experience taping out large SOC systems with embedded processor cores.
- Hands-on verification experience of PCIe Bus Fabric NOC AHB AXI based bus architecture in UVM environment.
- In-depth knowledge and experience working with low power design UPF integration boot-up power-cycling HW/FW interaction verification.
- Low Power Verification experience is a plus.
- Should be a phenomenal teammate with excellent communication and problem-solving skills and the desire to seek diverse challenges.
Employment Type
Full Time
Key Skills
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