Responsibility:
high-speed clock bus solutions and drive technology evolution within and between dies to meet extreme PPA (Power Performance Area) requirements of product projects.
physical design methodology research and technology evolution to build physical design competitiveness in multi-die scenarios such as 2.5D and 3D (Chiplet 3DIC) including but not limited to:
(1)Cross-die floorplan clock interconnect/bus power delivery and thermal management
(2)Development and implementation of cross-die physical design signoff methodologies
(3)Establishment of 3DIC reliability analysis methodologies
on physical design lead or participate in end-to-end STCO/DTCO efforts driving the development and evolution of Design Methodology tools related to physical design.
Requirenment:
1. Technical Expertise Requirements
(1) Proficient in back-end physical implementation with hands-on experience in high-speed physical design flows and tools; participated in large-scale chip physical implementation and physical verification projects.
(2) Proven experience in the planning or delivery of high-speed clock buses or Chiplet/3DIC designs.
(3) Familiar with characteristics of mainstream semiconductor processes with process analysis capabilities.
(4) Capable of translating market requirements into product planning and overall chip architecture definition.
(5) Skilled in physical architecture planning physical design and signoff for Chiplet/3DIC systems.
2. Educational Requirements
(1) Masters degree or above
(2) Major in Electronics Communications Computer Science Mathematics Automation Materials Science Physics or other related fields.
3. Work Experience
510 years of relevant experience
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