STA engineer
Posted on :
02-08-2025
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1 Vacancy
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Job Description
You will be responsible for:Develop/support automated block and full chip level signoff flowsFull Chip Timing/Noise convergence and full signoff for high quality TOEnable hierarchical Timing flowsPower optimizationsGenerate block level budget and context for correlation with Full ChipDrive custom IP integration and custom timing checks flowsClose work with Design DFT architecture and Power team
- 4 years experience in Static Timing analysis
- Extensive experience with one of the commercial STA tools
- Familiarity with hierarchical design approach top-down design timing and physical convergence
- Experience with backend STA closure and Signoff
- Deep understanding of designs constraints development
- Good understanding of AC timing from specs to implementation
- Good understanding of DFT modes and their constraints
- Good communication skills and team player
- Quick learning of flows and methods
- Advantage - Understanding noise and signal integrity effects
- Advantage - Timing margins fundamental from synthesis to signoff
- Advantage - Experience with scripting
Employment Type
Full Time
Key Skills
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