Senior Post-Silicon Product Engineer, Silicon Systems Group

Come join Amazon Devices and work within Amazon Lab126 where top engineers researchers and scientists invent design and build Amazons new consumer electronics devices and services. Amazon Lab126 has produced the bestselling Kindle devices the ground breaking Fire tablets and Fire TV and the revolutionary Echo.

We are seeking a seasoned Senior PostSilicon Product Engineer to lead and execute critical postsilicon validation characterization and production ramp activities for our advanced semiconductor products. This role demands a deep understanding of the semiconductor product lifecycle from initial silicon bringup to highvolume manufacturing ensuring product performance quality and reliability meet the highest standards.

Our final product is a complete consumer electronics system not just the silicon. As a PostSilicon Product Engineer youll go beyond traditional product engineering boundaries to address systemlevel challengesoffering rich opportunities to understand and influence system architecture and enduser performance.


Key job responsibilities

PostSilicon Validation & Characterization:
Lead the bringup and characterization of new silicon ensuring functionality and performance meet design specifications.
Develop and execute detailed validation plans including defining test methodologies coverage metrics and corner conditions.
Define and validate silicon and ATElevel test coverage ensuring comprehensive validation aligned with customer application scenarios.

Data Analysis & Yield Improvement:
Analyze data from WAT wafer sort ATE and systemlevel tests to identify trends anomalies and systematic issues.
Implement automation pipelines for data analysis across the test flow to improve traceability rootcause identification and feedback into design and test.
Develop and implement strategies that align test environments and methodologies with defined yield quality and performance objectives.
Apply advanced data analyticsincluding regression correlation and predictive modellingto optimize test efficiency and drive yield improvements.

Test Development & Optimization:
Collaborate with design and test engineering teams to develop and optimize test programs for wafer and packagelevel testing.
Partner with ATE engineers to debug test failures refine test coverage and identify limitations in test hardware/software infrastructure.
Lead test time reduction and cost optimization initiatives while maintaining required test coverage and quality standards.

CrossFunctional Collaboration:
Collaborate with Design SoC DFT Reliability Quality and Manufacturing teams to resolve silicon issues and support successful product ramp.
Lead structured failure analysis and root cause investigations to address quality reliability and customerreturn issues.
Coordinate with crossfunctional leaders to ensure alignment on key product KPIs such as yield DPPM quality escapes and production readiness.

Documentation & Reporting:
Generate comprehensive engineering reports detailing validation results failure analyses and recommended actions.
Maintain accurate records of test methodologies data analyses and process changes.

Bachelors or Masters degree in Electrical Engineering or a related field.
Minimum 10 years of experience in postsilicon validation product engineering or semiconductor development roles.
Strong understanding of semiconductor testing methodologies including ATE wafer sort and SLT.
Handson experience with silicon bringup validation characterization and debug.
Proficiency in data analysis tools such as JMP Python and SQL.
Familiarity with statistical methods such as SPC CPK DOE and other yield improvement methodologies.
Strong problemsolving skills including root cause analysis across silicon package and system levels.
Excellent written and verbal communication skills with the ability to document complex technical findings clearly.
Experience working in highvolume manufacturing environments supporting NPI (New Product Introduction) to mass production transition.

Experience with reliability testing standards (e.g. HTOL HAST TC) and failure analysis methodologies.
Knowledge of wafer fabrication and packaging processes.
Familiarity with defining test coverage for critical IP blocks and validating against customer use cases.
Experience using AWS cloud tools including Lambda functions SageMaker and QuickSight for data analysis and automation.
Exposure to systemlevel validation including correlation between silicon behavior and systemlevel performance.
Experience collaborating with SoC Design DFT Debug Leads Reliability and Quality teams.
Strong understanding of customer RMA handling and product sustenance strategies.
Experience with endtoend product ownership from early silicon evaluation through to highvolume production.

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