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Design Verification Engineer - 30607
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Design Verification ....
drjobs Design Verification Engineer - 30607 العربية

Design Verification Engineer - 30607

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1 Vacancy
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Job Location

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Re - Italy

Monthly Salary

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Not Disclosed

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Salary Not Disclosed

Vacancy

1 Vacancy

Job Description

Req ID : 2691342

Job Description

He/She will be expected to specify design/architect and implement stateoftheart Verification environments for the Design Ware family of synthesizable cores and perform Verification tasks for the IP cores. Candidate will work closely with RTL designers and be part of a global team of experienced Verification Engineers.
Job role will have a combination of Test planning Test environment coding both at unit level and system level Test case coding and debugging FC coding and review and meeting quality metric goals and regression management.
Key Qualification
  • BS/MS in EE/EC with 7 years of relevant experience in the verification of IP cores and/or SOC
  • Must have proven experience in developing HVL (System Verilog/UVM) based test environments developing and implementing test plans implementing and extracting verification metrics such as functional coverage and Code coverage.
  • Experience on DDR Protocol is necessary. Understanding of BIST would be added advantage.
  • Exposure to IP design and verification processes including VIP development is an added advantage.
  • Good communication skills debug and problem solving skills and should be self motivated
Experience: 7 yrs

Education/Experience

Preferred Experience
  • Be a technical contributor in the Verification Tasks &ndash System Verilog/Verilog coding of testbenches Test cases performing verification tasks such as coverage debug regressions using the latest methodologies such as UVM.
  • Creates deliverables which do not require close review or supervision by a Senior Technical Engineer
  • Be able to study the coverage metrics and improve them with definition of additional test cases in directed environment at least for small/ medium complexity features of the protocol/ product specs
  • Familiarity with HDLs such as Verilog and scripting languages such as shell/Perl/Python etc. is highly desirable
  • Works in a project and team oriented environment with teams spread across multiple sites worldwide.

Job Summary

About the Recruiter/Company





design ware family,ip design,verification environments,uvm,bist,python,test environment coding,perl,protocol,vip development,ddr protocol,hdls,ip cores,shell,recruitment,test planning,debug and problem solving skills,verilog,rtl designers,system verilog,design

Employment Type

Full Time

About Company

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