DFT engineer
DFT engineer
Posted on :
04-01-2024
Employer Active
1 Vacancy
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Jobs by Experience
3-5years
Monthly Salary
Not Disclosed
Salary Not Disclosed
Vacancy
1 Vacancy
Posted on :
04-01-2024
Job Description
Req ID : 2433318
o Working experience in SOC or Subsystems designs for multiple projects
o Strong understanding of DFT methodologies and experience in standard DFT tools.
Familiarity with SoC style DFT architectures including multiclock domain and low power
design practices.
Knowledge of DFT including Scan MBIST
Knowledge of low power design methodology (static/dynamic clock gating power gating
dynamic voltage and frequency scaling)
Good experience Toplevel clock/reset circuit design
Knowledge on DFT simulations and debugging.
Hands On experience in ATPG/SCAN/MBIST/JTAG implementation at chip & block level.
Knowledge on Test mode timing constraint development and analysis is a plus.
Understanding of test compression and ATE debug is a plus
Scan/ATPG: Exposure to Tessent tools and pattern generation/sim/debug and coverage improvement activities. Min experience of 3 years DFT DV: Candidates with Verif background and SV/UVM or C/C++ knowledge. Min experience of 3 years. Exposure to Scan, MBIST, BScan, JTAG verif would be an added advantage DFT RTL: Candidates with min 3 years experience in RTL integration and quality checks like Spyglass, LINT, CDC, etc.
Employment Type
Full Time
Key Skills
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