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Mid-Level SoC Design Verification Engineer

Best NanoTech


Job Location:

Hyderabad - India

Monthly Salary: Not provided by the employer
Posted: 22 May 2026 (30+ days ago)
Application Deadline: 19 August 2026
Vacancies: 1 Vacancy
The job posting is outdated and position may be filled

Job Summary

Mid-Level SoC Design Verification Engineer
  • Hyderabad India
  • Full-Time Onsite
  • 6 8 Years
Role Overview

Looking for a Mid-Level SoC Verification Engineer with strong experience in ARM-based SoC verification and Arm Corestone platforms. The role involves subsystem verification UVM-based environment development protocol verification debugging and collaboration with design and architecture teams.

Key Responsibilities
  • Verify ARM-based SoC subsystems and integrations
  • Develop DV test plans test benches and testcases
  • Build SystemVerilog/UVM verification environments
  • Perform functional verification and coverage closure
  • Debug simulation and integration issues
  • Work with AXI/AHB/APB-based subsystem verification
  • Support gate-level simulation and low-power verification
  • Collaborate with architecture RTL and ATE teams
  • Generate VCD/FSDB files for power analysis and testing
Required Qualifications
  • Bachelors/Masters degree in Electronics Electrical or Computer Engineering
  • 6 8 years of SoC/ASIC verification experience
  • Strong expertise in ARM architecture and AMBA protocols
  • Hands-on experience with Arm Corestone platforms
  • Good experience in SystemVerilog and UVM
  • Familiarity with Cadence simulation tools
  • Strong debugging and verification skills
Technical Skills
  • ARM Architecture
  • Arm Corestone
  • ASIC SoC Verification
  • SystemVerilog / UVM
  • AXI / AHB / APB Protocols
  • Test Bench Development
  • Functional Verification
  • Cadence Tools
  • Gate-Level Simulation
  • C/C and Verilog
  • AI/ML SoC exposure
  • Low-power verification experience
  • ATE pattern generation support

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