FPGA Lead
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Monthly Salary:
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Job Summary
Role : FPGA Lead:
Experiecne : 8-15years:
Notice Period : Immediate to 30 Days
Work Mode : 5 Days office
Job Description (JD):
We are seeking a highly skilled and experienced RTL Design Engineer with a strong knowledge of AMD-Xilinx FPGA this role you will design Register-Transfer Level (RTL) Intellectual Property (IP) with a focus on video connectivity subsystems. You will have dynamic multi-faceted responsibilities in areas such as project definition RTL design and implementation. You will participate in the design architecture documentation and implementation of the low latency video connectivity systems. You will be also responsible for RTL coding of blocks specified by you or others. Additionally you will be responsible for various front-end methodology flows that include resource optimization clock domain crossing and reset domain crossing.
Qualifications:
Must have proven experience working on Video domain IPs / Digital IPs.
Must have proven experience working of one or more protocols at the IP level: MIPI CSI / MIPI DSI / DisplayPort /HDMI / SDI.
Hands on experience with AMD/Xilinx FPGA device and Vivado toolchain.
Hands on experience with architecting / micro-architecture / detailed design from functional specifications.
Hands on experience with Synthesizable Verilog/ System Verilog RTL coding for FPGA designs.
Lint CDC synthesis flow and static timing flows formal checking etc. experience.
Working knowledge / experience in TCL Perl Python is an added advantage.
SERDES architecture knowledge is a plus.
Has a solid desire to learn and explore new technologies.
Strong communication and presentation skills.
Close collaboration with different teams across various time zones.
