Wireless SOC Design Verification Engineer

Apples N1 wireless chip powers connectivity across every new iPhone and its successor is already taking shape. As a Senior Wireless SOC Verification Engineer youll own your verification scope end-to-end on each project from test planning through signoff. Over time youll grow in two directions: deeper into the IPs and subsystems you know best or broader across different IPs and subsystems and across levels from block verification up to top-level SOC integration. That choice plays out project to project not within a single one.

Youll own your verification scope end-to-end real stakes real ownership on a chip that ships in every new iPhone. Youll work across the Power Management Unit the CPU subsystem on-chip debug infrastructure PCIe bus fabric boot and secure-boot sequencing and peripherals like SPI and UART choosing simulation formal or whichever approach the design actually calls for. Low-power isnt just a block though its part of your scope wherever it shows up: youll verify power intent using UPF within your area not just inside one IP. AI is already reshaping how we work. The team is pushing hard on AI-assisted verification and youll help figure out where it fits best whether thats test generation debug verification closure or all of the above rather than inheriting a playbook someone else already wrote.

Pair with design early shape the verification plan before RTL lands not corner-case failures and build the models coverage or proof that catch low-power design intent using UPF within your into formal verification as your projects call for it. The team will help you ramp up not expect you to arrive methodology decisions in your area you set the approach not just execute end-to-end WiFi and Bluetooth traffic flows from subsystem level up through top-level SOC on AI-assisted verification help the team find where it moves the post-silicon bring-up when your project needs it.

BS and a minimum of 10 years relevant industry track record of working full ASIC cycle from concept to tape-out to bring-up including test-planning testbench implementation test sequence creation and debugging and coverage in SystemVerilog coding and UVM methodology.

Hands-on verification experience of PCIe Bus Fabric NOC AHB AXI-based bus architecture in UVM verifying IP or top-level integration for a WiFi or Bluetooth with Formal -depth knowledge and experience working with low power design UPF integration boot-up power-cycling HW/FW interaction taping out large SOC systems with embedded processor be a great teammate with excellent communication and problem-solving skills and the desire to seek diverse challenges.