Voltus-FI, EMIR, Sr Application Engineer

At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.

Key Responsibilities

• Drive customer adoption of Cadence Quantus signoff parasitic extraction and VoltusFi EMIR solutions through guided presales and postsales technical engagements.
• Support and execute customer benchmarks and evaluations to demonstrate product accuracy performance and value under supervision.
• Develop and deliver technical demonstrations product presentations and proofofconcepts with mentoring from senior team members.
• Collaborate with sales management account teams and customers to understand technical requirements and support business opportunities.
• Contribute to technical sales execution plans while communicating progress and learnings to peers and field technical management.
• Provide presales technical support during customer meetings evaluations and presentations to help drive successful design wins.

Minimum Qualifications

• Masters degree in Electrical Engineering Computer Engineering or a related technical discipline.
• Academic coursework or internship experience in VLSI design physical design or signoff flows including exposure to parasitic extraction EMIR timing or physical verification concepts.
• Basic understanding of IC layout netlists LVS and signoff methodologies.
• Familiarity with Linux/UNIX environments and EDA tool workflows.
• Strong analytical and problemsolving skills with the ability to debug technical issues with guidance.
• Good written and verbal communication skills with interest in customerfacing technical roles.
• Ability to work effectively in a teamoriented fastpaced environment and collaborate with sales R&D and field teams.

Preferred Qualifications

• Exposure to Cadence tools such as Quantus VoltusFi Virtuoso Pegasus or Spectre through coursework academic projects or internships.
• Coursework or project experience related to advanced semiconductor technologies power integrity signal integrity or physical verification.
• Internship or handson project experience involving EDA tools semiconductor design flows or foundry PDKs.
• Basic scripting knowledge in Tcl Python or shell scripting for flow automation or data analysis.

Strong interest in technical customer engagement including demos evaluations and product enablement

The annual salary range for California is $84000 to $156000. You may also be eligible to receive incentive compensation: bonus equity and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications skill level competencies and work location. Our benefits programs include: paid vacation and paid holidays 401(k) plan with employer match employee stock purchase plan a variety of medical dental and vision plan options and more.

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