The SRAM / NVM (Non-Volatile Memory) DFT Technologist leads and develops the engineering solution for testing verifying and validating post-silicon memory test solutions (from characterization to HVM). This role focuses on building robust DFT architectures for SRAM / NVM with a balanced focus on automotive quality and cost-of-test optimization. Will require driving EDA vendors to improve NVM test capabilities aid customers in NVM selection/tradeoffs repair optimizations HVM bitmap solutions and debug silicon issues.
Your Job:
Own developing the engineering solutions for testing verifying and validating post-silicon memory test solutions (from characterization to HVM).
Define and deploy end-to-end test architecture from design insertion through silicon validation covering all aspects of SRAM / NVM technologies including but not limited to MRAM and RRAM.
Develop and optimize SRAM / NVM testing balancing coverage test time and yield learning.
Customize testing solutions to balance customer quality and test cost goals.
Own post-silicon test planning including validation vectors ATE correlation and silicon bring-up strategies.
Interface closely with design verification product engineering and ATE teams to ensure smooth handoff from simulation to tester.
Develop automated test programs and diagnostic scripts supporting wafer sort package test and system-level characterization.
Analyze silicon test data for root-cause isolation yield improvement and continuous methodology refinement.
Document test specifications qualification methodologies and re-use frameworks for ongoing improvement.
Other Responsibilities:
Coaches and mentors less experienced staff; influences others as a technical leader.
Familiarity with reliability testing and failure analysis specific to NVM devices.
Perform all activities in a safe and responsible manner and support all Environmental Health Safety & Security requirements and programs
Required Qualifications:
Bachelors or Masters degree in Electrical Engineering Computer Engineering or a related field.
15 years of hands-on experience across silicon lifecycle DFT design implementation validation and post-silicon characterization to HVM.
Expert in MBIST / NVM testing is a must with a proven record of driving EDA vendor improvements and engaging with customers to debug silicon issues.
Practical experience with post-silicon silicon debug ATE vector bring-up (e.g. Teradyne Advantest) and yield analysis.
Ability to correlate pre-silicon and production test environments including diagnostic log analysis and tester pattern debug.
Proficiency with major EDA tools (Synopsys Cadence Siemens/Mentor) and scripting (Python Perl TCL).
Strong understanding of test coverage metrics fault simulation and data-driven test improvements.
Excellent technical leadership planning and communication skills across cross-functional teams.
Preferred Qualifications:
Strategic thinker who understands full-lifecycle testfrom design to production ramp.
Innovative leader who drives collaboration between design EDA fab and product engineering.
Passionate about test time reduction yield learning and driving cost-effective test solutions.
Continuous learner who proactively evaluates tools methods and automation opportunities.
Expected Salary Range
$171000.00 - $296000.00
The exact Salary will be determined based on qualifications experience and location.
If you need a reasonable accommodation for any part of the employment process please contact us by email at and let us know the nature of your request and your contact information. Requests for accommodation will be considered on a case-by-case basis. Please note that only inquiries concerning a request for reasonable accommodation will be responded to from this email address.
An offer with GlobalFoundries is conditioned upon the successful completion of pre-employment conditions as applicable and subject to applicable laws and regulations.
GlobalFoundries is fully committed to equal opportunity in the workplace and believes that cultural diversity within the company enhances its business potential. GlobalFoundries goal of excellence in business necessitates the attraction and retention of highly qualified people. Artificial barriers and stereotypic biases detract from this objective and may be illegally discriminatory.
All policies and processes which pertain to employees including recruitment selection training utilization promotion compensation benefits extracurricular programs and termination are created and implemented without regard to age ethnicity ancestry color marital status medical condition mental or physical disability national origin race religion political and/or third-party affiliation sex sexual orientation gender identity or expression veteran status or any other characteristic or category specified by local state or federal law
Required Experience:
IC
The SRAM / NVM (Non-Volatile Memory) DFT Technologist leads and develops the engineering solution for testing verifying and validating post-silicon memory test solutions (from characterization to HVM). This role focuses on building robust DFT architectures for SRAM / NVM with a balanced focus on aut...
The SRAM / NVM (Non-Volatile Memory) DFT Technologist leads and develops the engineering solution for testing verifying and validating post-silicon memory test solutions (from characterization to HVM). This role focuses on building robust DFT architectures for SRAM / NVM with a balanced focus on automotive quality and cost-of-test optimization. Will require driving EDA vendors to improve NVM test capabilities aid customers in NVM selection/tradeoffs repair optimizations HVM bitmap solutions and debug silicon issues.
Your Job:
Own developing the engineering solutions for testing verifying and validating post-silicon memory test solutions (from characterization to HVM).
Define and deploy end-to-end test architecture from design insertion through silicon validation covering all aspects of SRAM / NVM technologies including but not limited to MRAM and RRAM.
Develop and optimize SRAM / NVM testing balancing coverage test time and yield learning.
Customize testing solutions to balance customer quality and test cost goals.
Own post-silicon test planning including validation vectors ATE correlation and silicon bring-up strategies.
Interface closely with design verification product engineering and ATE teams to ensure smooth handoff from simulation to tester.
Develop automated test programs and diagnostic scripts supporting wafer sort package test and system-level characterization.
Analyze silicon test data for root-cause isolation yield improvement and continuous methodology refinement.
Document test specifications qualification methodologies and re-use frameworks for ongoing improvement.
Other Responsibilities:
Coaches and mentors less experienced staff; influences others as a technical leader.
Familiarity with reliability testing and failure analysis specific to NVM devices.
Perform all activities in a safe and responsible manner and support all Environmental Health Safety & Security requirements and programs
Required Qualifications:
Bachelors or Masters degree in Electrical Engineering Computer Engineering or a related field.
15 years of hands-on experience across silicon lifecycle DFT design implementation validation and post-silicon characterization to HVM.
Expert in MBIST / NVM testing is a must with a proven record of driving EDA vendor improvements and engaging with customers to debug silicon issues.
Practical experience with post-silicon silicon debug ATE vector bring-up (e.g. Teradyne Advantest) and yield analysis.
Ability to correlate pre-silicon and production test environments including diagnostic log analysis and tester pattern debug.
Proficiency with major EDA tools (Synopsys Cadence Siemens/Mentor) and scripting (Python Perl TCL).
Strong understanding of test coverage metrics fault simulation and data-driven test improvements.
Excellent technical leadership planning and communication skills across cross-functional teams.
Preferred Qualifications:
Strategic thinker who understands full-lifecycle testfrom design to production ramp.
Innovative leader who drives collaboration between design EDA fab and product engineering.
Passionate about test time reduction yield learning and driving cost-effective test solutions.
Continuous learner who proactively evaluates tools methods and automation opportunities.
Expected Salary Range
$171000.00 - $296000.00
The exact Salary will be determined based on qualifications experience and location.
If you need a reasonable accommodation for any part of the employment process please contact us by email at and let us know the nature of your request and your contact information. Requests for accommodation will be considered on a case-by-case basis. Please note that only inquiries concerning a request for reasonable accommodation will be responded to from this email address.
An offer with GlobalFoundries is conditioned upon the successful completion of pre-employment conditions as applicable and subject to applicable laws and regulations.
GlobalFoundries is fully committed to equal opportunity in the workplace and believes that cultural diversity within the company enhances its business potential. GlobalFoundries goal of excellence in business necessitates the attraction and retention of highly qualified people. Artificial barriers and stereotypic biases detract from this objective and may be illegally discriminatory.
All policies and processes which pertain to employees including recruitment selection training utilization promotion compensation benefits extracurricular programs and termination are created and implemented without regard to age ethnicity ancestry color marital status medical condition mental or physical disability national origin race religion political and/or third-party affiliation sex sexual orientation gender identity or expression veteran status or any other characteristic or category specified by local state or federal law
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