Senior Technical Staff Engineer Design (IO)

Are you looking for a unique opportunity to be a part of something great Want to join a 17000-member team that works on the technology that powers the world around us Looking for an atmosphere of trust empowerment respect diversity and communication How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization We offer all that and more at Microchip Technology Inc.

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Job Description:

Job Description:

The successfulcandidate will join the rapidly growing Data Center Solutions (DCS) business unit at Microchip. DCS has a broad portfolio of products widely deployed by the industrys cutting-edge server/storage OEMs and hyperscale datacenters. Customers deploy DCS solutions into applications ranging from Big Data capacity storage to artificial intelligence and machine learning that are helping to shape the next digital age. Our product portfolio includes SAS/PCIe/NVMe/CXL products that connect manage and secure the worlds information including Flash Controllers High Performance Switches RAID Controllers and Memory Controllers. Join a team where you can expand your skill set and drive key elements of the industrys technology leadership.

An opening exists for Tech Staff/Sr. Staff IO Design Engineer with an interest in developing the next generation of storage and memory controller SoC products. This will involve taking a design from initial concept through to production. Throughout you will work beside experienced engineers and be exposed to Microchips Best-In-Class engineering practices. Working side-by-side with some of the brightest minds and most innovative people in the industry you wont just fill a position you will be given an opportunity to work on a team where your contributions matter. Microchip fosters continuous learning in a challenging and rewarding environment. If this sounds like the kind of environment youd like to participate in wed like to hear from you!

As a Staff/ Design Engineer your job will entail the following:

• Design planning of pad rings and package substrates bump pattern construction.

• Dynamically define and optimize pad ring connectivity.

• Work with CFTs (Cross-Functional Team) on the deliverables (DEF Verilog netlist etc.)

• Interface with and support Architect PD PE technology development and foundries teams.

• Support JTAG TAP controller integration and implementation across SoC designs ensuring IEEE 1149.1 compliance and proper JTAG signal connectivity in collaboration with the DFT team.

• Collaborate with CFTs on TAP controller operation scan-enable path handling and post-silicon debug requirements.

• Support Verification Emulation ASIC lab validation including lab debug and providing logic modifications and workarounds.

Requirements/Qualifications:

• B.S or M.S degree in electrical engineering with 12 years related experience.

• Hands-on experience with pad ring planning IO cell placement and bump map/pattern definition for advanced SoC designs.

• Knowledge of IO library cells IO standards and PHY-level IO interfaces (SerDes DDR PCIe CXL).

• Experience with IO planning and implementation EDA tools (e.g. Orbit IO ISP or equivalent); specific tool experience is valuable but not mandatory.

• Experience generating and validating IO connectivity deliverables (pad ring DEF IO netlist bump assignment) for physical design hand-off).

• Experience with Verilog/System Verilog is required.

• Basic to intermediate knowledge of JTAG/Boundary Scan (IEEE 1149.1) architecture and TAP controller operation.

• Hands-on experience with DFT methodologies is a plus and considered equivalent familiarity.

• Familiarity with JTAG-based post-silicon debug flows and bring-up strategies for SoC IO validation.

• Experience with boundary scan cell behavior and test access port (TAP) signal verification is a plus.

• Scripting experience or knowledge is a plus.

• Excellent analytical communication (written and verbal) and documentation skills.

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Benefits of working at Microchip

Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex gender identity sexual orientation race color religion national origin disability protected Veteran status age or any other characteristic protected by law.

For more information on applicable equal employment regulations please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster.

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